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悟禅的行者 发表于 2011-4-18 15:58:13

用Verilog编的基于FPGA的交通灯的程序，请求帮忙修改注释

各位大侠，首先声明我不是偷懒，实在是迫于压力无奈，今年毕业，不从事本专业，找了一篇论文（不是完整的），语言是VHDL的，但我只接触过Verilog,用转换器转换了一下，但有很多错误，马上就要交论文了，请大家帮帮忙，修改和注释一下程序（简单的声明语句就不用注释了），在此谢过各位！

欲设计有一条主干道和一条支干道的汇合点形成十字交叉路口，主干道为东西向，支干道为南北向。为确保车辆安全，迅速地通行，在交叉道口的每个入口处设置了红，绿，黄3色信号灯。具体要求如下：
（1）主干道绿灯亮时，支干道红灯亮，反之亦然，两者交替允许通行，主干道每次放行55s，支干道每次放行25s。每次由绿灯变为红灯的过程中，黄灯亮5s作为过渡。
（2）能实现正常的倒计时显示功能。
（3）能实现总体清零功能：计数器由初始状态开始计数，对应状态的指示灯亮。
（4）能实现特殊状态的功能显示：进入特殊状态时，东西、南北路口均显示红灯状态。

主干道绿灯55sec，支干道绿灯25sec，黄灯5sec过渡。同时用数码管指示当前状态（红、黄、绿）剩余时间。另外，设计一个紧急状态，当紧急状态出现时，两个方向都禁止通行，指示红灯。紧急状态解除后，指示紧急状态前的时间。当复位状态出现时，整个系统恢复起始状态。当主干道绿灯55秒和5秒黄灯过渡时，支干道必须禁止通行，即支干道红灯亮55+5=60秒；当支干道由红灯转为绿灯时，支干道亮25秒绿灯和5秒黄灯过渡，此时主干道红灯应亮25+5=30秒。

module traffic(clk,reset,sp,GA,YA,RA,ring,pin129,GB,YB,RB,BCDout,LEDout);
input clk;
input reset;
input sp;
output GA;
wire GA;
output YA;
wire YA;
output RA;
wire RA;
inout ring;
wire ring_xhd10;
inout pin129;
wire pin129_xhdl1;
output GB;
wire GB;
output YB;
wire YB;
output RB;
wire RB;
output BCDout;
wire BCDout;
out LEDout;
wire a0;
wire a1;
integer b;
integer d;
integer e;
integer f;
integer g;
integer h;

assign ring=ring_xhdl0;
assign pin129=pin129_xhdl1;

div u1(
.clkin1(clk),
.clkout1(a0)
);
div u2(
.clkin2(a0),
.clkout1(a1)
);
counter u3(
.clock(a1),
.reset(reset),
.sp(sp),
.countNum(b)
);
controller u4(
.clock(a1),
.countNum(b),
.sp(sp),
.GreenA(GA),
.YellowA(YA),
.RedA(RA),
.GreenB(GB),
.YellowB(YB),
.RedB(RB),
.NumA(c),
.NumB(d)
);
fenwei1 u5(
.Numin(c),
.NumA(e),
.NumB(f)
);
fenwei2 u6(
.Numin(d),
.NumC(g),
.NumD(h)
);
demx u7(
.clock(a0),
.NumA(e),
.NumB(f),
.NumC(g),
.NumD(h),
.segout(BCDout),
.led_sel(LEDout)
);

assign ring=1’b;
assign pin129=1’b1;
endmodule
module div1(clkin1,clkout1);

input clkin1;
output clkout1;
wire clkout1;
parameter N=1000;
reg counter;
reg clk;

always@(clkin1)
begin
if(clkin1==1b’1)
begin
if(counter==N)
   begin
      counter<=1;
      clk<= ~clk;
   end
else
   begin
      counter<= counter+1;
   end
end
end

assign clkout1=CLK;
endmoule

module div2(clkin2,clkout2);
input clkin2;
output clkout2;
parameter N=500;
reg counter;

always@(clkin2)
begin
if(clkin2==1’b1)
   begin
      if(counter==N);
         begin
            counter<=1;
            clk<= ~clk;
         end
      else
         begin
            counter<= counter+1;
         end
end
end

assign clkout2=CLK;
endmoule

module counter(clock,reset,sp,countNum);
input clock;
input reset;
input sp;
output countNum;
reg countNum;

always@( reset or clock or sp)
begin
if(reset= =1’b0)
   begin
         countNum<=0;
   end
else
   begin
if(clock= =1’b1)
   begin
      if(sp= =1’b0)
            begin
                  countNum<= countNum;
            end
      else
            begin
               if(countNum= =91)
                  begin
                     countNum<=0;
                  end
               else
                  begin
                     countNum<= countNum+1;
                  end
         end
      end
end
end
endmodule

module controller(clock,sp,countnum,NumA,NumB,RedA,GreenA,YellowA, RedB,GreenB,YellowB);
input clock;
input sp
input countnum;
output NumA;
reg NumA;
output NumB;
reg NumB;
output RedA;
reg RedA;
output GreenA;
reg GreenA;
output YellowA;
reg YellowA;
output RedB;
reg RedB;
output GreenB;
reg GreenB;
output YellowB;
reg YellowB;

always@(clock or sp)
begin
   if(sp= =1’b0)
         begin
            RedA<=1’b1;
            RedB<=1’b1;
            GreenA<=1’b0;
            GreenB<=1’b0;
            YellowA<=1’b0;
            YellowB<=1’b0;
         end
   else if(clock= =1’b1)
begin
if(countnum<=55)
   begin
      NumA<=55- countnum;
      RedA<=1’b0;
      GreenA<=1’b1;
      YellowA<=1’b0;
   end
      else if(countnum<=60);
         begin
      NumA<=60- countnum;
      RedA<=1’b0;
      GreenA<=1’b0;
      YellowA<=1’b1;
   end
else
   begin
      NumA<=91- countnum;
      RedA<=1’b1;
      GreenA<=1’b0;
      YellowA<=1’b0;
   end
if(countnum<=60)
   begin
      NumB<=60- countnum;
      RedB<=1’b1;
      GreenB<=1’b0;
      YellowB<=1’b0;
   end
else if(countnum<=86)
   begin
      NumB<=60- countnum;
      RedB<=1’b1;
      GreenB<=1’b0;
      YellowB<=1’b0;
   end
else
   begin
      NumB<=91- countnum;
      RedB<=1’b0;
      GreenB<=1’b0;
      YellowB<=1’b1;
   end
      end
end
endmodule

分位器模块主程序
module fenwei1(Numin,NumA,NumB);
inputNumin;
outputNumA;
regNumA;
outputNumB;
regNumB;

always@(Numin)
begin
if(Numin>=50)
begin
   NumA<=5;
   NumB<= Numin-50;
end
else if(Numin>=40)
begin
   NumA<=4;
   NumB<= Numin-40;
end
else if(Numin>=30)
begin
   NumA<=3;
   NumB<= Numin-30;
end
else if(Numin>=20)
begin
   NumA<=2;
   NumB<= Numin-20;
end
else if(Numin>=10)
begin
   NumA<=1;
   NumB<= Numin-10;
end
else
begin
   NumA<=0;
   NumB<= Numin;
end
end
endmodule

module fenwei2(Numin,NumC,NumD);
inputNumin;
outputNumC;
regNumC;
outputNumD;
regNumD;

always@(Numin)
begin
if(Numin>=60)
   begin
   NumC<=6;
   NumD<= Numin-60;
   end
else if(Numin>=50)
begin
   NumC<=5;
   NumD<= Numin-50;
   end
else if(Numin>=40)
   begin
   NumC<=4;
   NumD<= Numin-40;
   end
else if(Numin>=30)
   begin
   NumC<=3;
   NumD<= Numin-30;
   end
else if(Numin>=20)
   begin
   NumC<=2;
   NumD<= Numin-20;
   end
else if(Numin>=10)
   begin
   NumC<=1;
   NumD<= Numin-10;
   end
else
begin
   NumC<=0;
   NumD<= Numin;
   end
end
endmodule

BCD数码管模块主程序
module demx(clock,NumA, NumB, NumC, NumD,segout,led_sel);
input clock;
intput NumA;
intput NumB;
intput NumC;
intput NumD;
outputsegout;
wiresegout;
outputled_sel;
reg led_sel;
integer Q1;
regQ2;

always@(clock)
begin
if(clock= =1’b1)
begin
   Q2<=Q2+1’b1;
end
end

always@(Q2 or NumA or NumB or NumC or NumD)
begin
case(Q2)
2’b00:
         begin
            led_sel<=4’b0001;
            Q1<=NumD;
         end
2’b01:
            begin
            led_sel<=4’b0010;
               Q1<=NumC;
            end
2’b10:
            begin
            led_sel<=4’b0100;
               Q1<=NumB;
            end
2’b11:
            begin
            led_sel<=4’b1000;
               Q1<=NumA;
            end
   default:
            begin
            end
endcase
end
BCD u1(
.bcd.data(Q1),
.bcdout(segout)
);
endmodule

module BCD(bcd_data,bcdout);
input bcd_data;
output bcdout;
reg bcdout;

always@(bcd_data)
begin
case(bcd_data)
0:
   begin
            bcdout<=8’b11000000;
         end
1:
   begin
            bcdout<=8’b11110000;
         end
2:
   begin
            bcdout<=8’b10100100;
         end
3:
   begin
            bcdout<=8’b10110000;
         end
4:
   begin
            bcdout<=8’b10011001;
         end
5:
   begin
            bcdout<=8’b10000010;
         end
6:
   begin
            bcdout<=8’b10000010;
         end
7:
   begin
            bcdout<=8’b11111000;
         end
8:
   begin
            bcdout<=8’b10000000;
         end
9:
   begin
            bcdout<=8’b10010000;
         end
default:
begin
end
endcase
end
endmoule

顶层文件模块主程序
module traffic(clk,reset,sp,GA,YA,RA,ring,pin129,GB,YB,RB,BCDout,LEDout);
input clk;
input reset;
input sp;
output GA;
wire GA;
output YA;
wire YA;
output RA;
wire RA;
inout ring;
wire ring_xhd10;
inout pin129;
wire pin129_xhdl1;
output GB;
wire GB;
output YB;
wire YB;
output RB;
wire RB;
output BCDout;
wire BCDout;
out LEDout;
wire LEDout;

wire a0;
wire a1;
integer b;
integer d;
integer e;
integer f;
integer g;
integer h;

assign ring=ring_xhdl0;
assign pin129=pin129_xhdl1;

div u1(
   .clkin1(clk),
   .clkout1(a0)
);
div u2(
   .clkin2(a0),
   .clkout1(a1)
);
counter u3(
   .clock(a1),
   .reset(reset),
   .sp(sp),
   .countNum(b)
);
controller u4(
      .clock(a1)，
      .countNum(b)，
      .sp(sp),
      .GreenA(GA),
      .YellowA(YA),
      .RedA(RA),
      .GreenB(GB),
      .YellowB(YB),
      .RedB(RB),
      .NumA(c),
      .NumB(d)
);
fenwei1 u5(
      .Numin(c),
      .NumA(e),
      .NumB(f)
);
fenwei2 u6(
      .Numin(d),
      .NumC(g),
         .NumD(h)
);
demx u7(
   .clock(a0),
   .NumA(e),
   .NumB(f),
   .NumC(g),
   .NumD(h),
   .segout(BCDout),
   .led_sel(LEDout)
);
assign ring=1’bz;
assign pin129=1’b1;
endmodule

悟禅的行者 发表于 2011-4-20 09:30:18

没人吗，呜呜

18799730091 发表于 2021-6-29 17:01:32

这个代码是好使的吗https://cdn.jsdelivr.net/gh/hishis/forum-master/public/images/patch.gif

lihongkun16 发表于 2021-6-30 09:28:27

用Verilog编的基于FPGA的交通灯的程序，请求帮忙修改注释

dameihuaxia 发表于 2021-7-7 14:12:09

FPGA全局时钟的运用
http://www.fpgaw.com/forum.php?mod=viewthread&tid=136175&fromuid=58166
(出处: fpga论坛|fpga设计论坛)

页: [1]

fpga论坛|fpga设计论坛's Archiver

用Verilog编的基于FPGA的交通灯的程序，请求帮忙修改注释