Verilog HDL Unsigned Multiply-Accumulator
Example 12-5: Verilog HDL Unsigned Multiply-Accumulatormodule unsig_altmult_accum (dataout, dataa, datab, clk, aclr, clken);
input dataa, datab;
input clk, aclr, clken;
output reg dataout;
reg dataa_reg, datab_reg;
reg multa_reg;
wire multa;
wire adder_out;
assign multa = dataa_reg * datab_reg;
assign adder_out = multa_reg + dataout;
always @ (posedge clk or posedge aclr)
begin
if (aclr)
begin
dataa_reg <= 8'b0;
datab_reg <= 8'b0;
multa_reg <= 16'b0;
dataout <= 17'b0;
end
else if (clken)
begin
dataa_reg <= dataa;
datab_reg <= datab;
multa_reg <= multa;
dataout <= adder_out;
end
end
endmodule 8位乘法器的写法，ALTERA的代码 谢谢分享。。。。。。。。。。。。。。:lol
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