论坛 › FPGA技术交流 › Altera 推荐的SystemVerilog Simple Dual-Port Synchronous RAM with Byte Enable

陈飞龙 发表于 2017-10-17 16:43:27

Altera 推荐的SystemVerilog Simple Dual-Port Synchronous RAM with Byte Enable

SystemVerilog Simple Dual-Port Synchronous RAM with Byte Enable

module byte_enabled_simple_dual_port_ram
(
input we, clk,
input waddr, raddr, // address width = 6
input be, // 4 bytes per word
input wdata, // byte width = 8, 4 bytes per word
output reg q // byte width = 8, 4 bytes per word
);
// use a multi-dimensional packed array
//to model individual bytes within the word
logic ram; // # words = 1 << address width
always_ff@(posedge clk)
begin
if(we) begin
if(be) ram <= wdata;
if(be) ram <= wdata;
if(be) ram <= wdata;
if(be) ram <= wdata;
end
q <= ram;
end
endmodule

陈飞龙 发表于 2017-10-17 16:44:24

Altera推荐的RAM双端口写发

zhangyukun 发表于 2017-10-18 10:09:51

Altera 推荐的SystemVerilog Simple Dual-Port Synchronous RAM with Byte Enable

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