新手急求！！！！！望高手给与解答，跪求，高手给指点迷津!!!!!!!！！！！
新手急求！！！！！望高手给与解答module count10a(outa,couta,en,clk,rst);
output outa;
output couta;
regcountb;
reg couta;
assign outa=countb;
input clk,rst,en;
always@(*)
if(!rst) begin
countb<=4'b0;
couta<=1'b0;
end
else
if(en)
begin
if(countb==9)
begin
countb<=4'b0;
couta<=~couta;
end
else
begin
countb<=countb+1;
end
end
else
begin
countb<=4'b0;
couta<=1'b0;
end
endmodule
在用quartus编译的时候出现这个警告：Warning: Verilog HDL Always Construct warning at count10a.v(9): variable "couta" may not be assigned a new value in every possible path through the Always Construct.Variable "couta" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.希望高手给与解决的方案，警告出现在红字上面 把这个语句always@(*)替换成always @ (posedge clk or negedge rst)试一下！
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