求路过大侠解答~~~~
LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_signed.ALL;
ENTITY key_sync IS
PORT (key_in :IN std_logic;
clk :IN std_logic;
key_out :OUTstd_logic);
END key_sync;
ARCHITECTURE Behavioral OF key_sync IS
COMPONENT dff
PORT (clk :IN std_logic;
d :IN std_logic;
q :OUTstd_logic;
qn :OUTstd_logic);
END COMPONENT dff;
SIGNAL tmp1 :std_logic;
SIGNAL tmp2 :std_logic;
SIGNAL tmp3 :std_logic;
SIGNAL tmp4 :std_logic;
SIGNAL tmp5 :std_logic;
SIGNAL tmp6 :std_logic;
BEGIN
tmp2 <=key_in NAND tmp1;
tmp1 <=tmp3 NAND tmp2;
key_out <=tmp4 AND tmp5;
U1: dff
PORT MAP(clk,tmp2,tmp4,tmp3);
U2: dff
PORT MAP(clk,tmp4,tmp6,tmp5);
END Behavioral;
文中有2处错误，说qn不在dff VHDL DESIGN 文件夹中
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