源码分享：出租车计费器的 FPGA Verilog源代码
module fp50m(clk,reset,newclk,newclk1);input clk,reset;output newclk,newclk1；
reg newclk,newclk1;reg count,count1;
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
newclk<=1'd0;
count<=32'd0;
end
else if(count==32'd25000000)
begin
count<=32'd0;
newclk<=~newclk;
end//end begin
else count<=count+1'd1;
end
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
newclk1<='d0;
count1<=32'd0;
end
else if(count1==32'd100000)
begin
count1<=32'd0;
newclk1<=~newclk1;
end
else
count1<=count1+1'd1;
endendmodule
module distance(clk,start,reset,run,distance,distance_enable);
input clk,start,reset,run;
output distance;
reg distance;
output distance_enable;
reg distance_enable;
always@(posedge clk or negedge reset)
begin
if(!reset)
distance<=8'd0;
else if(!start) distance<=8'd0;
else
begin if (run)
begin if(distance==9)//判断distance的低四位记到了9没
begin distance<=4'd0;//记到则清零
if(distance==9) //判断高四位记到9没
distance<=4'd0;// 记到则清零
else distance<=distance+1'd1;// distance的高四位没有记到9则加1
end//end else
distance<=distance+1'd1;// distance的低四位没有记到9则加1
end//end always
end
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
distance_enable<=1'd0;
end
else if(distance>8'd1)
begin
distance_enable<=1'd1;
end//end begin
end//end always
endmodule
module wait_time(clk,reset,start,run,s,m);
input clk,reset,run,start;
output s;
output m;
reg s;
reg m;
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
s<=8'd0; m<=8'd0;
end
else if(!start)
begin
s<=8'd0; m<=8'd0;
end
else if(run)
begin
s<=8'd0; m<=8'd0;
end
else
begin
if(s==9)// 秒的低四位是9
begin
s<=4'd0;//清零
if(s==5) // 秒的高四位是5
begin
s<=4'd0; //清零
if(m==9) // 分的低四位是9
begin
m<=4'd0; //清零
if(m==9) // 分的高四位是9
m<=4'd0; //清零
else m<=m+1'd1; // 分的高四位不是9加1
end
else
m<=m+1'd1; //分的低四位不是9加1
end
else s<=s+1'd1; // 秒的高四位不是5加1
end
else s<=s+1'd1; //秒的低四位不是9加1
end
end//end always
endmodule
module charge(clk, //50MHz run, distance_enable, day_enable,start, //启动reset,distance, //里程wait_time, //等待时间charge );
input clk,day_enable,distance_enable,run;input start,reset;
wire price_day_time,price_day_distance,price_night_time,price_night_distance,fee;
wire one_price_day,one_price_night;
input distance;input wait_time;
output charge;reg one_price;
wire wait_time;reg cnt1; //白天短里程
reg cnt2; //白天长里程
reg cnt3; //晚上短里程
reg cnt4; //晚上长里程
wire charge;
assign price_day_time=1;
assign price_day_distance=2;
assign price_night_time=2;
assign price_night_distance=4;
assign one_price_day=5;
assign one_price_night=7;
assign fee=4;
assign charge=one_price+cnt1*price_day_time+cnt2*price_day_distance+cnt3*price_night_time+cnt4*price_night_distance+fee;
always@(posedge clk or negedge reset)
begin
if(!reset) //清零
begin
cnt1<=0;cnt2<=0;cnt3<=0;
cnt4<=0;
one_price<=0;
end
else begin
if(!start)
begin
cnt1<=0;
cnt2<=0;
cnt3<=0;
cnt4<=0;
one_price<=0;
end
else
begin
if(day_enable)
one_price<=one_price_day;
else
one_price<=one_price_night;
begin
if(day_enable && run==1'b0)
begin
if(!run)
begin
cnt1<=wait_time;
end
if(distance_enable)
cnt2<=distance-3'd3;
end
else
begin
if(!run)
cnt3<=wait_time;
if(distance_enable)
cnt4<=distance-3;
end
end
end
end
end
endmodule
module seg(clk,data_in,data_out,addr_out);
input clk;
input data_in;
output data_out;
output addr_out;
wire n4,n3,n2,n1;
reg data;
reg data_out,code=0;reg addr,addr_out;
reg flag=0;
assign n4=data_in;
assign n3=data_in;
assign n2=data_in;
assign n1=data_in;
always @(posedge clk)
begin
case(flag)
2'd3:
begin data<=n4;
addr<=4'b0111;
end
2'd2:
begin data<=n3;
addr<=4'b1011;
end
2'd1:
begin
data<=n2;
addr<=4'b1101;
end
2'd0:
begin data<=n1;
addr<=4'b1110;
end
endcase
flag<=flag+1'b1;
if(flag>3)
flag<=0;
case(data)
8'd0: code<=7'b1111110;
8'd1: code<=7'b0110000;
8'd2: code<=7'b1101101;
8'd3: code<=7'b1111001;
8'd4: code<=7'b0110011;
8'd5: code<=7'b1011011;
8'd6: code<=7'b1011111;
8'd7: code<=7'b1110000;
8'd8: code<=7'b1111111;
8'd9: code<=7'b1111011;
endcase
data_out<=~code;
addr_out<=addr;
end
endmodule
module control(clk_50M, reset,start,run,day_enable,duan,wei,key1,key2);
input clk_50M,reset,start,run;
input day_enable,key1,key2;
wire distance,s,m;
wire charge;
wire clk,distance_enable,time_enable,newclk1;
output duan;
output wei;
reg data;
always@(posedge clk or negedge reset)
begin
if(!reset)
data<=16'd0;
else
begin
if(!start)
data<=16'd0;
else
begin
if(key1)
begin
data <= distance;
end
else
if(key2)
begin
data <= m; data <= s;
end
else
data <=charge;
end
end
end
taxitop c1(clk_50M, reset,start,run,distance,s,m,charge,clk,day_enable,distance_enable,newclk1);
seg u1(newclk1,data,duan,wei);
endmodule
module taxitop(clk_50M, reset,start,run,distance,s,m,charge,clk,day_enable,distance_enable,newclk1);
input clk_50M,reset,start,day_enable,run;
output s,m,charge,distance;
output clk,distance_enable,newclk1;
wire distance;wire s;
wire m;
wire charge;
wire price_day_time,price_day_distance,price_night_time,price_night_distance, price_wait_time,one_price_day,one_price_night,fee;
wire distance_enable;
wire day_enable;
wire clk,newclk1;
fp50m u1(.clk(clk_50M),.reset(reset),.newclk(clk),.newclk1(newclk1));
distance u2(clk,start,reset,run,distance,distance_enable);
wait_time u3(clk,reset,start,run,s,m);charge u5(clk_50M,run,distance_enable,day_enable,start,reset,distance,m,charge);
endmodule 源码分享：出租车计费器的 FPGA Verilog源代码 源码分享：出租车计费器的 FPGA Verilog源代码 源码分享：出租车计费器的 FPGA Verilog源代码 源码分享：出租车计费器的 FPGA Verilog源代码 源码分享：出租车计费器的 FPGA Verilog源代码 源码分享：出租车计费器的 FPGA Verilog源代码 源码分享：出租车计费器的 FPGA Verilog源代码
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