jpg4151 发表于 2011-5-26 20:06:30

书上的例子运行有误，请各位指教

`timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
begin
            wave=0;
#(cycle/2)wave=1;
#(cycle/2)wave=0;
#(cycle/2)wave=1;
#(cycle/2)wave=0;
#(cycle/2)wave=1;
#(cycle/2)$finish ;
end
initial $monitor($time,,,"wave=%b",wave);
endmodule


Error: Can't synthesize current design -- Top partition does not contain any logic
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 4 warnings
        Error: Peak virtual memory: 170 megabytes
        Error: Processing ended: Thu May 26 19:41:29 2011
        Error: Elapsed time: 00:00:06
        Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 4 warnings

至芯兴洪 发表于 2011-5-26 21:40:41

这是一段用于测试的模块，不可综合

wangxia6112 发表于 2011-5-27 09:58:52

这是测试程序，是配合功能模块使用的，以便测试你的程序是否正确。

wolfson 发表于 2011-5-27 15:31:53

always语句可以综合，initial语句不能被综合。
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