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j123m456 发表于 2011-6-6 11:42:17

怎么理解这句话

wireclk_5ms=&count;

icewan11 发表于 2011-6-13 00:00:56

& : This is a bitwise-AND operator. It performs an AND function on
the operands to return a value that is equivalent in bus width to the
operands.

参考资料:<<Verilog.Coding.for.Logic.Synthesis>> a john Wiley & sons. publish

------count的所有位进行“与”运算，结果赋给clk_5ms;

j123m456 发表于 2011-6-13 15:38:59

我重新看了书，原来是缩减运算··

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