移位指令SLL和SLA怎么用?出错了,不知道错在哪里……
SIGNAL Q : STD_LOGIC_VECTOR(15 DOWNTO 0);……
……
PROCESS(a,b)
BEGIN
FOR n IN 0 to 7 LOOP
b_extend(0) <= b(n);
Q <= a_extend * b_extend;
Q <= Q SLL n;
sum <= sum+Q;
END LOOP;
END PROCESS;
上面是源程序
下面是出错信息:
Error (10327): VHDL error at multipier8bit9_16.vhd(23): can't determine definition of operator ""sll"" -- found 0 possible definitions 直接用移位符号不可以么? SIGNAL Q,p : STD_LOGIC_VECTOR(15 DOWNTO 0);
……
……
PROCESS(a,b)
BEGIN
FOR n IN 0 to 7 LOOP
b_extend(0) <= b(n);
Q <= a_extend * b_extend;
p <= Q SLL n;
sum <= sum+p;
END LOOP;
END PROCESS; 算术移位:SLA(算术左移),SRA(算术右移),空缺位用当前为补充;
逻辑移位:SLL(逻辑左移),SRL(逻辑右移),空缺位补0。 回复 3# 伯尼
还是不行啊……题目要求是利用循环语句和一位操作符实现移位相加方式的纯组合电路8位乘法器的设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY multipier8bit9_16 IS
PORT( a,b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sum : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY multipier8bit9_16;
ARCHITECTURE one OF multipier8bit9_16 IS
SIGNAL Q,p: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL a_extend : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL b_extend : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
Q <= (OTHERS => '0');
sum <= (OTHERS => '0');
a_extend <= (OTHERS => '0');
b_extend <= (OTHERS => '0');
a_extend(7 DOWNTO 0) <= a(7 DOWNTO 0);
PROCESS(a,b)
BEGIN
FOR n IN 0 to 7 LOOP
b_extend(0) <= b(n);
Q <= a_extend * b_extend;
p <= Q SLL n; --shouwei shi '0',bu '0'; shi '1',bu '1'
sum <= sum + p;
END LOOP;
END PROCESS;
END ARCHITECTURE one;
这是完整的源程序,下面是出错信息:
Error (10327): VHDL error at multipier8bit9_16.vhd(23): can't determine definition of operator ""sll"" -- found 0 possible definitions 回复 2# ppc68
直接用了操作符出现了这个错误:
Error (10327): VHDL error at multipier8bit9_16.vhd(23): can't determine definition of operator ""sll"" -- found 0 possible definitions 回复 4# 伯尼
这个我知道,查了资料,但是会出现这个错误,我不知道为什么会出现这个错误:
Error (10327): VHDL error at multipier8bit9_16.vhd(23): can't determine definition of operator ""sll"" -- found 0 possible definitions 难道是没加库? 回复 8# ppc68
加了!上面我把完整的程序粘贴过来了! 遇到相同问题,有没有答案啊?
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