求高手解释
本帖最后由 qq181022849 于 2011-6-16 21:12 编辑我用matlab设计个butterworth滤波器这个图是得到的一些数据请问这些数据就是这个4*6的矩阵在我的程序中是怎么用的？？我给老师说是ise处理不了小数，她说我说的不对，不知道怎么给她解释
程序
Testbench.v是测试工程；
Butterworth.v是顶层文件；
Sub2.v是第二层文件。
2.1 Butterworth.v
`timescale 1ns / 1ps
module butterworth(
clk,
reset,
x_in,
y_out
);
input clk;
input reset;
input x_in;
output y_out;
wire y1_out;
wire y2_out;
wire y3_out;
// the coefs of the filter
wire a_1,a_2;
wire b1_1_1,b1_2_1;
wire b2_1_1,b2_2_1;
wire b3_1_1,b3_2_1;
wire b4_1_1,b4_2_1;
assign a_1 = 16'b0100000000000000;
assign a_2 = 16'b0010000000000000;
assign b1_1_1 = 16'b1101111110000011;
assign b1_2_1 = 16'b0001011101000111;
assign b2_1_1 = 16'b1110011000001100;
assign b2_2_1 = 16'b0000110000100111;
assign b3_1_1 = 16'b1110100110000011;
assign b3_2_1 = 16'b0000011001000011;
assign b4_1_1 = 16'b1110101100000110;
assign b4_2_1 = 16'b0000001110110000;
sub2 sub2_1(.clk(clk),.reset(reset),.a_1_1(a_1),.a_2_1(a_2),.b_1_1(b1_1_1),.b_2_1(b1_2_1),.x_in(x_in),.y_out(y1_out));
sub2 sub2_2(.clk(clk),.reset(reset),.a_1_1(a_1),.a_2_1(a_2),.b_1_1(b2_1_1),.b_2_1(b2_2_1),.x_in(y1_out),.y_out(y2_out));
sub2 sub2_3(.clk(clk),.reset(reset),.a_1_1(a_1),.a_2_1(a_2),.b_1_1(b3_1_1),.b_2_1(b3_2_1),.x_in(y2_out),.y_out(y3_out));
sub2 sub2_4(.clk(clk),.reset(reset),.a_1_1(a_1),.a_2_1(a_2),.b_1_1(b4_1_1),.b_2_1(b4_2_1),.x_in(y3_out),.y_out(y_out));
endmodule
2.2 Sub2.v
`timescale 1ns / 1ps
module sub2(
clk,
reset,
a_1_1,
a_2_1,
b_1_1,
b_2_1,
x_in,
y_out
);
input clk;
input reset;
input a_1_1;
input a_2_1;
input b_1_1;
input b_2_1;
input x_in;
output y_out;
reg x_temp;
reg y_temp;
reg y_out;
wire p1,p2,p3,p4,p5;
wire y_t;
MULTIPLY mult1(.dataa(x_temp),.datab(a_2_1),.result(p1));
MULTIPLY mult2(.dataa(x_temp),.datab(a_1_1),.result(p2));
MULTIPLY mult3(.dataa(x_in),.datab(a_2_1),.result(p3));
MULTIPLY mult4(.dataa(y_temp),.datab(b_2_1),.result(p4));
MULTIPLY mult5(.dataa(y_temp),.datab(b_1_1),.result(p5));
always@(posedge clk)
begin
if(!reset)
begin
x_temp <= 0;
y_temp <= 0;
end
else
begin
x_temp <= {x_temp,x_in};
y_temp <= {y_temp,y_out};
end
if(y_t== 3'b000 ||y_t== 3'b111 )
y_out <= y_t;
else if(y_t == 1)
y_out <= 16'b 1000000000000000;
else
y_out <= 16'b 0111111111111111;
end
assign y_t = reset? ({p1,p1} + {p2,p2} + {p3,p3} - {p4,p4} - {p5,p5}):0;
//assign y_out = {y_t,y_t};
Endmodule
2.3 Testbench.v
`timescale 1 ps/ 1 ps
module testbench();
reg clk;
reg reset;
reg x_in;
wire y_out;
reg memory ;
reg i;
integer x_datain;
integer y_dataout;
initial
begin
reset = 0;
clk = 0;
i= 0;
#50 reset = 1;
x_in = 0;
x_datain =$fopen("sourceData.txt","r");
$readmemb("sourceData.txt",memory);
y_dataout = $fopen("finalData.txt","w");
$display("Running testbench");
end
always #1 clk = ~clk;
always@(posedge clk)
begin
if(i==10'd1000)
begin
i <= 0;
end
else
i <= i+1;
x_in <=memory;
$display("%b\n",y_out);
//$fdisplay(y_dataout,"\n%b",y_out);
end
butterworth i1(
.clk(clk),
.reset(reset),
.x_in(x_in),
.y_out(y_out)
);
endmodule
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