verilog实现及仿真
m_sequence.v(以x8+x4+x3+x2+1为例) tips：代码实现依据原理方框图和特征多项式。<span style="font-size:14px;">module m_sequence(
input sclk,
input rst_n,
output wire m_seq
);
parameter POLY = 8'b10001110;//由本原多项式得到
reg shift_reg;
always@(posedge sclk or negedge rst_n)
begin
if(rst_n == 0)begin
shift_reg <= 8'b11111111;//初值不可为全零
end
else begin
shift_reg <= (shift_reg & POLY)^
(shift_reg & POLY)^
(shift_reg & POLY)^
(shift_reg & POLY)^
(shift_reg & POLY)^
(shift_reg & POLY)^
(shift_reg & POLY)^
(shift_reg & POLY);
shift_reg <= shift_reg;
end
end
assign m_seq = shift_reg;
endmodule</span>
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