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njithjw 发表于 2011-7-16 22:32:39

除法器

`timescale 1ns/1ns
module divider
    (
    input               clk,
    input               rst,
    input          dividend,
    input          divisor,
    input               load,

    outputreg    ratio,
    outputreg    remainder,
    outputreg         finish
    );

reg      cnt;
reg   dividend_widen;
reg      ratio_shift;
wire       sub;
wire    dividend_shift;
always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
      cnt <= 4'd15;
    else if (load == 1'b1)
      cnt <= 4'd0;
    else
      cnt <= cnt + {3'd0,~(&cnt)};
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
      dividend_widen <= 17'd0;
    else if (load == 1'b1)
      dividend_widen <= {9'd0,dividend};
    else
      dividend_widen <= dividend_shift;
end

assign sub = dividend_widen - divisor;
assign dividend_shift = (sub == 1'b0)? {sub,dividend_widen,1'b0}: {dividend_widen,1'b0};

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
      ratio_shift <= 8'd0;
    else
      ratio_shift <= {ratio_shift,~sub};
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
      ratio <= 8'd0;
    else if (cnt == 4'd9)
      ratio <= ratio_shift;
    else ;
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
      remainder <= 8'd0;
    else if (cnt == 4'd9)
      remainder <= dividend_widen;
    else ;
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
      finish <= 1'b0;
    else if (cnt == 4'd9)
      finish <= 1'b1;
    else
      finish <= 1'b0;
end

endmodule

蓝余 发表于 2011-7-17 14:58:46

好贴，顶一个！~

liujilei311 发表于 2011-7-17 21:29:26

的确是好帖，顶一个！！！！

derksyq 发表于 2011-12-6 23:27:20

写的些什么呀 代码真难看 除数为0 都没写一个error报错 直接用移位相减不是更简单 这有超前借位提速吗
如果换成64位/32位 这个算法比移位相减速度快吗

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