求助
下面这个文件使用modelsim仿真怎么总是提示语法错误啊？高手帮我看看：module divfre
(clk,
divclk);
input clk;
output divclk;
reg divclk;
reg counter;
initial
begin
divclk=0;
counter=0;
end
always @(posedge clk)
begin
begin
if (counter>=5'b110001)
counter<=0;
else counter<=counter+1;
end
divclk<=counter;
end
endmodule
错误提示：syntax error
页:
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