RISC CPU-时序 发生器设计
module clk_gen (clk,reset,clk1,clk2,clk4,fetch,alu_clk);2 input clk,reset;
3 output clk1,clk2,clk4,fetch,alu_clk;
4 wire clk,reset;
5 reg clk2,clk4,fetch,alu_clk;
6 reg state;
7 parameter S1 = 8'b00000001,
8 S2 = 8'b00000010,
9 S3 = 8'b00000100,
10 S4 = 8'b00001000,
11 S5 = 8'b00010000,
12 S6 = 8'b00100000,
13 S7 = 8'b01000000,
14 S8 = 8'b10000000,
15 idle = 8'b00000000;
16 assign clk1 = ~clk;
17
18 always @(negedge clk)
19 if(reset)
20 begin
21 clk2 <= 0;
22 clk4 <= 1;
23 fetch <= 0;
24 alu_clk <= 0;
25 state <= idle;
26 end
27 else
28 begin
29 case(state)
30 S1:
31 begin
32 clk2 <= ~clk2;
33 alu_clk <= ~alu_clk;
34 state <= S2;
35 end
36 S2:
37 begin
38 clk2 <= ~clk2;
39 clk4 <= ~clk4;
40 alu_clk <= ~alu_clk;
41 state <= S3;
42 end
43 S3:
44 begin
45 clk2 <= ~clk2;
46 state <= S4;
47 end
48 S4:
49 begin
50 clk2 <= ~clk2;
51 clk4 <= ~clk4;
52 fetch <= ~fetch;
53 state <= S5;
54 end
55 S5:
56 begin
57 clk2 <= ~clk2;
58 state <= S6;
59 end
60 S6:
61 begin
62 clk2 <= ~clk2;
63 clk4 <= ~clk4;
64 state <= S7;
65 end
66 S7:
67 begin
68 clk2 <= ~clk2;
69 state <= S8;
70 end
71 S8:
72 begin
73 clk2 <= ~clk2;
74 clk4 <= ~clk4;
75 fetch <= ~fetch;
76 state <= S1;
77 end
78 idle: state <= S1;
79 default: state <= idle;
80 endcase
81 end
82 endmodule RISC CPU-时序 发生器设计
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