RISC CPU 算术运算器
module alu (alu_out, zero, data, accum, alu_clk, opcode);3 output alu_out;
4 output zero;
5 input data, accum;
6 input opcode;
7 input alu_clk;
8 reg alu_out;
9
10 parameter HLT =3’b000,
11 SKZ =3’b001,
12 ADD =3’b010,
13 ANDD =3’b011,
14 XORR =3’b100,
15 LDA =3’b101,
16 STO =3’b110,
17 JMP =3’b111;
18
19 assign zero = !accum;
20 always @(posedgealu_clk)
21 begin //操作码来自指令寄存器的输出opc_iaddr<15..0>的低3位
22 casex (opcode)
23 HLT: alu_out<=accum;
24 SKZ: alu_out<=accum;
25 ADD: alu_out<=data+accum;
26 ANDD: alu_out<=data&accum;
27 XORR: alu_out<=data^accum;
28 LDA: alu_out<=data;
29 STO: alu_out<=accum;
30 JMP: alu_out<=accum;
31 default: alu_out<=8'bxxxx_xxxx;
32 endcase
33 end
34 endmodule
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