RISC CPU-状态控制器
module machinectl( ena, fetch, rst);3 output ena;
4 input fetch, rst;
5 reg ena;
6 always @(posedge fetch or posedge rst)
7
8
9 begin
10 if(rst)
11 ena<=0;
12 else
13 ena<=1;
14 end
15 endmodule
module machine( inc_pc, load_acc, load_pc, rd,wr, load_ir,
3 datactl_ena, halt, clk1, zero, ena, opcode );
4 output inc_pc, load_acc, load_pc, rd, wr, load_ir;
5 output datactl_ena, halt;
6 input clk1, zero, ena;
7 input opcode;
8 reg inc_pc, load_acc, load_pc, rd, wr, load_ir;
9 reg datactl_ena, halt;
10 reg state;
11
12 parameter HLT = 3 'b000,
13 SKZ = 3 'b001,
14 ADD = 3 'b010,
15 ANDD = 3 'b011,
16 XORR = 3 'b100,
17 LDA = 3 'b101,
18 STO = 3 'b110,
19 JMP = 3 'b111;
20
21 always @( negedge clk1 )
22 begin
23 if ( !ena ) //接收到复位信号RST，进行复位操作
24 begin
25 state<=3'b000;
26 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
27 {wr,load_ir,datactl_ena,halt}<=4'b0000;
28 end
29 else
30 ctl_cycle;
31 end
32 //-----------------begin of task ctl_cycle---------
33 task ctl_cycle;
34 begin
35 casex(state)
36 3’b000: //load high 8bits in struction
37 begin
38 {inc_pc,load_acc,load_pc,rd}<=4'b0001;
39 {wr,load_ir,datactl_ena,halt}<=4'b0100;
40 state<=3’b001;
41 end
42 3’b001: //pc increased by one then load low 8bits instruction
43 begin
44 {inc_pc,load_acc,load_pc,rd}<=4'b1001;
45 {wr,load_ir,datactl_ena,halt}<=4'b0100;
46 state<=3’b010;
47 end
48 3’b010: //idle
49 begin
50 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
51 {wr,load_ir,datactl_ena,halt}<=4'b0000;
52 state<=3’b011;
53 end
54 3’b011: //next instruction address setup 分析指令从这里开始
55 begin
56 if(opcode==HLT) //指令为暂停HLT
57 begin
58 {inc_pc,load_acc,load_pc,rd}<=4'b1000;
59 {wr,load_ir,datactl_ena,halt}<=4'b0001;
60 end
61 else
62 begin
63 {inc_pc,load_acc,load_pc,rd}<=4'b1000;
64 {wr,load_ir,datactl_ena,halt}<=4'b0000;
65 end
66 state<=3’b100;
67 end
68 3’b100: //fetch oprand
69 begin
70 if(opcode==JMP)
71 begin
72 {inc_pc,load_acc,load_pc,rd}<=4'b0010;
73 {wr,load_ir,datactl_ena,halt}<=4'b0000;
74 end
75 else
76 if( opcode==ADD || opcode==ANDD ||
77 opcode==XORR || opcode==LDA)
78 begin
79 {inc_pc,load_acc,load_pc,rd}<=4'b0001;
80 {wr,load_ir,datactl_ena,halt}<=4'b0000;
81 end
82 else
83 if(opcode==STO)
84 begin
85 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
86 {wr,load_ir,datactl_ena,halt}<=4'b0010;
87 end
88 else
89 begin
90 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
91 {wr,load_ir,datactl_ena,halt}<=4'b0000;
92 end
93 state<=3’b101;
94 end
95 3’b101: //operation
96 begin
97 if ( opcode==ADD||opcode==ANDD||opcode==XORR||opcode==LDA )
98 begin //过一个时钟后与累加器的内容进行运算
99 {inc_pc,load_acc,load_pc,rd}<=4'b0101;
100 {wr,load_ir,datactl_ena,halt}<=4'b0000;
101 end
102 else
103 if( opcode==SKZ && zero==1)
104 begin
105 {inc_pc,load_acc,load_pc,rd}<=4'b1000;
106 {wr,load_ir,datactl_ena,halt}<=4'b0000;
107 end
108 else
109 if(opcode==JMP)
110 begin
111 {inc_pc,load_acc,load_pc,rd}<=4'b1010;
112 {wr,load_ir,datactl_ena,halt}<=4'b0000;
113 end
114 else
115 if(opcode==STO)
116 begin
117 //过一个时钟后把wr变1就可写到RAM中
118 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
119 {wr,load_ir,datactl_ena,halt}<=4'b1010;
120 end
121 else
122 begin
123 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
124 {wr,load_ir,datactl_ena,halt}<=4'b0000;
125 end
126 state<=3’b110;
127 end
128 3’b110: //idle
129 begin
130 if ( opcode==STO )
131 begin
132 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
133 {wr,load_ir,datactl_ena,halt}<=4'b0010;
134 end
135 else
136 if ( opcode==ADD||opcode==ANDD||opcode==XORR||opcode==LDA)
137 begin
138 {inc_pc,load_acc,load_pc,rd}<=4'b0001;
139 {wr,load_ir,datactl_ena,halt}<=4'b0000;
140 end
141 else
142 begin
143 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
144 {wr,load_ir,datactl_ena,halt}<=4'b0000;
145 end
146 state<=3’b111;
147 end
148 3’b111: //
149 begin
150 if( opcode==SKZ && zero==1 )
151 begin
152 {inc_pc,load_acc,load_pc,rd}<=4'b1000;
153 {wr,load_ir,datactl_ena,halt}<=4'b0000;
154 end
155 else
156 begin
157 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
158 {wr,load_ir,datactl_ena,halt}<=4'b0000;
159 end
160 state<=3’b000;
161 end
162 default:
163 begin
164 {inc_pc,load_acc,load_pc,rd}<=4'b0000;
165 {wr,load_ir,datactl_ena,halt}<=4'b0000;
166 state<=3’b000;
167 end
168 endcase
169 end
170 endtask
171 //-----------------end of task ctl_cycle---------
172 endmodule
173 //------------------------------------------------------------------------------ RISC CPU-状态控制器
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