视频解码后保存到sram中进行读写的问题
这是本人写的关于将视频解码后的YCbCr422中一帧图像的亮度信号Y保存到sram中，写完一帧后从sram读出进行后续分析的verilog HDL代码。现在的问题是输出的数据仅仅是最后一个数据，而地址却是逐渐累加的，没发现什么错误。希望高手们给分析一下，不胜感激！！！ VGA分辨率640*480sram是256*16 的。最后可以帮忙改正一下。module sram_c5(
VGA_VS,
VGA_HS,
iclk,
swit,
Yw,
sram_addr,
sram_data,
sram_oe_n,
sram_ce_n,
sram_we_n,
sram_lb_n,
sram_ub_n,
led,
sram_odata,
);
input VGA_VS;
input VGA_HS;
input Yw;
input iclk;
output sram_addr;
inout sram_data;
input swit;
outputsram_oe_n,sram_ce_n,sram_we_n,sram_lb_n,sram_ub_n;
output led;
output sram_odata;
wire sram_oe_n1;
wire sram_we_n1;
wire sram_we_n2;
wire sram_oe_n2;
wire con;
wire sram_data,sram_idata,sram_odata;
wire sram_addr1,sram_addr2;
sram_wr sram_wr(
.iclk(iclk),
.Yw(Yw),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.sram_data(sram_data),
.swit(swit),
.sram_oe_n1(sram_oe_n1),
.sram_we_n1(sram_we_n1),
.sram_addr1(sram_addr1),
.con(con)
);
sram_rd sram_rd(
.swit(swit),
.iclk(iclk),
.sram_data(sram_data),
.sram_odata(sram_odata),
.led(led),
.sram_oe_n2(sram_oe_n2),
.sram_we_n2(sram_we_n2),
.sram_addr2(sram_addr2),
.con(con)
);
assign sram_ce_n=0;
assign sram_lb_n=0;
assign sram_ub_n=1;
assign sram_addr=(!con)?sram_addr1:sram_addr2;
assign sram_oe_n=(!con)?sram_oe_n1:sram_oe_n2;
assign sram_we_n=(!con)?sram_we_n1:sram_we_n2;
endmodule
// 下面是写的模块
module sram_wr(
sram_data,
Yw,
VGA_VS,
VGA_HS,
sram_addr1,
iclk,
swit,
sram_oe_n1,
sram_we_n1,
con
);
input iclk;
input Yw;
output sram_addr1;
input swit;
input VGA_VS;
input VGA_HS;
output sram_data;
output sram_oe_n1,sram_we_n1;
output con;
reg wr_data;
reg addr_r;
reg sram_we_n1;
reg sram_oe_n1;
//-----------------------下面的上升沿是为了检测一帧的开始------------------------------------------//
reg pluse_buf1;
reg pluse_buf2;
always @(posedge iclk)
begin
pluse_buf1<= VGA_VS;
pluse_buf2<=pluse_buf1;
end
assign pluse_raise1 = pluse_buf1& (~pluse_buf2);//-----------vs---------------
reg flag;
always@(posedge pluse_raise1) begin
if(!swit) flag<=0;
else begin
if(VGA_VS) flag<=1;
end
end
//-----------------------------------------------------
reg con;
always@(posedge iclk) begin
if(!swit) begin
wr_data<=8'd0;
addr_r<=18'd0;
con<=0;
sram_we_n1<=1;
sram_oe_n1<=1;
end
else if(!con) begin
if(flag) begin
if(VGA_VS) begin
if(VGA_HS) begin
sram_we_n1<=0;
sram_oe_n1<=1;
addr_r<=addr_r+1;
wr_data<=Yw;
end
end
else begin
con<=1;
end
end
end
end
assign sram_addr1=addr_r;
assign sram_data=(!sram_we_n1)?wr_data:8'hzz;
endmodule
下面是读的模块
module sram_rd(
swit,
sram_odata,
sram_data,
sram_addr2,
iclk,
con,
sram_oe_n2,
sram_we_n2,
led
);
input swit;
input iclk;
output sram_odata;
output sram_addr2;
input con;
input sram_data;
output sram_oe_n2,sram_we_n2;
output led;
reg rd_data;
reg addr_r;
reg sram_oe_n2;
wire VGA_4CLK;
reg cnt1;
always@(posedge iclk)
cnt1<=cnt1+1;
assign VGA_4CLK=cnt1;
reg cnt2;
always@(posedge VGA_4CLK) begin
if(con&&swit) cnt2<=cnt2+1;
else cnt2<=17'b0;
end
assign sram_we_n2=1;
always@(posedge VGA_4CLK) begin
if(con&&swit) begin
if(cnt2<17'd47) begin
sram_oe_n2<=0;
addr_r<=cnt2;
rd_data<=sram_data;
end
elsebegin
sram_oe_n2<=1;
rd_data<=8'h0;
end
end
end
assign sram_addr2=addr_r;
assign sram_odata=rd_data;
assign led=sram_odata;
endmodule 对verilog不太熟悉啊，不过还是要学习一下！！！！！！！！ 自己先顶顶 大家帮顶一下啊 让高手看见 拜托了 有没有知道原因的 急用啊 高手何在 出来帮一下小忙吧 有么有人知道问题出在哪啊 恩，好好学习一下！！！！ 将CNT2的累加和读取那块儿弄到一个always语句试试，我觉得有点儿问题 回复 9# 离场悲剧
好的 我先试试
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