这段代码编译没有问题，为什么综合却不行呢，各位高手帮忙看一下，问题出在哪？
------------------------------------------------------------------------------------ Company:
-- Engineer:
--
-- Create Date: 12:12:12 09/01/2011
-- Design Name:
-- Module Name: TimeSequenceWithDSP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TimeSequenceWithDSP is
Port ( Addr : inSTD_LOGIC_VECTOR (9 downto 1);
Data : inoutSTD_LOGIC_VECTOR (15 downto 0);
CSn : inSTD_LOGIC;
RD_WRn : inSTD_LOGIC;
RDn : inSTD_LOGIC;
WRHn : inSTD_LOGIC;
WRLn : inSTD_LOGIC;
WAITn : outSTD_LOGIC;
ena: out std_logic;
wea: out std_logic; -- interface with DRAM 0:read, 1:write
addra: out std_logic_vector(8 downto 0); -- interface with DRAM
dina: in std_logic_vector(15 downto 0);
douta: out std_logic_vector(15 downto 0)
);
end TimeSequenceWithDSP;
architecture Behavioral of TimeSequenceWithDSP is
begin
ena <= CSn;
addra(8 downto 0) <= Addr(9 downto 1);
wea <= (not RD_WRn);
process(RDn,WRLn,WRHn)begin
if(CSn = '0') then
if(RDn='1' and RDn' event) then
Data(15 downto 0) <= dina(15 downto 0);
else
if(WRLn='1' and WRLn' event) then
douta(7 downto 0) <= Data(7 downto 0);
end if;
if(WRHn='1' and WRHn' event) then
douta(15 downto 8) <= Data(15 downto 8);
end if;
end if;
else
Data(15 downto 0) <= (OTHERS => 'Z');
end if;
end process;
end Behavioral; 综合器报的什么错误啊，你没贴出来，编译没错就是代码没错啊。代码没错不代表综合不会出错。你把综合器报的错贴出来看看。 VHDL现在用的越来越少了，不懂，呵呵
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