inout使用中出现Illegal output or inout port connection (port 'a_in').
在练习verilog时碰到这样一个问题# ** Error: (vsim-3053) testTOP.v(19): Illegal output or inout port connection (port 'a_in').
# Region: /testTOP_v/test6
# ** Error: (vsim-3053) testTOP.v(19): Illegal output or inout port connection (port 'b_in').
# Region: /testTOP_v/test6
# ** Error: (vsim-3053) testTOP.v(19): Illegal output or inout port connection (port 'c_in').
# Region: /testTOP_v/test6
# ** Error: (vsim-3053) testTOP.v(19): Illegal output or inout port connection (port 'd_in').
# Region: /testTOP_v/test6
# Error loading design
我的verilog模块源代码为：
`timescale 1ns / 100ps
module test6(a_out,b_out,c_out,d_out,a_in,b_in,c_in,d_in);
output a_out,b_out,c_out,d_out;
inout a_in,b_in,c_in,d_in;
reg a_out,b_out,c_out,d_out;
reg at,bt,ct,dt;
always@(a_in or b_in or c_in or d_in)
begin
{at,bt,ct,dt}={a_in,b_in,c_in,d_in};
sort(at,ct);
sort(bt,dt);
sort(at,bt);
sort(ct,dt);
sort(bt,ct);
{a_out,b_out,c_out,d_out}={at,bt,ct,dt};
end
task sort;
inoutx,y;
regtemp;
if(x>y)
begin
temp=x;
x=y;
y=temp;
end
endtask
endmodule
我的test bench是：
`timescale 1ns / 1ps
`include "test6.v"
module testTOP_v;
// Outputs
wire a_out;
wire b_out;
wire c_out;
wire d_out;
// Bidirs
reg a_in;
reg b_in;
reg c_in;
reg d_in;
test6 test6 (.a_out(a_out), .b_out(b_out), .c_out(c_out), .d_out(d_out),
.a_in(a_in), .b_in(b_in), .c_in(c_in), .d_in(d_in));
initial
begin
a_in=0;
b_in=0;
c_in=0;
d_in=0;
repeat(50)
begin
#100
a_in={$random}%25;
b_in={$random}%25;
c_in={$random}%25;
d_in={$random}%25;
end
#3000 $stop;
end
endmodule 我也碰到同样问题。
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