程序错误
大家帮忙看看下面的程序，有错误，帮忙改改，万分感谢library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mycounter_60 is
port(clk,clr,en,bcd1wr,bcd10wr:in std_logic;
din:in std_logic_vector(3 downto 0);
bcd1: out std_logic_vector(3 downto 0);
co: out std_logic;
bcd10: out std_logic_vector(2 downto 0));
end mycounter_60;
architecture art2 of mycounter_60 is
signal bcd1n:std_logic_vector(3 downto 0);
signal bcd10n:std_logic_vector(2 downto 0);
begin
PROCESS(clk,clr,en,bcd1wr) is
begin
if(clr='0') then
bcd1n<=(others=>'0');
bcd10n<=(others=>'0');
elsif(clk'event and clk='1') then
if(bcd1wr='1' and en='1') then
bcd1n<=din;
elsif(en='1') then
bcd1n<=bcd1n+1;
if(bcd1n>=9) then
bcd1n<="0000";
end if;
end if;
end if;
end process;
process(bcd10wr,en,bcd1n) is
begin
if(bcd10wr='1' and en='1') then
bcd10n<=din(2 downto 0);
elsif(bcd1n=9 and en='1') then
bcd10n<=bcd10n+1;
if(bcd10n=5) then
bcd10n<="000";
co<='1';
else
co<='0';
end if;
end if;
end process;
bcd1<=bcd1n;
bcd10<=bcd10n;
end art2;
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