基于verilog的PWM实现
本帖最后由 fpgaw 于 2010-8-13 09:45 编辑基于verilog的PWM实现
module pwm (clk, write_data, cs, write_n, addr, clr_n, read_data, pwm_out);
input clk;
input write_data;
input cs;
input write_n;
input addr;
input clr_n;
output read_data;
output pwm_out;
// 定义period和pulse_width寄存器的内容
reg period;
reg pulse_width;
reg counter;
reg off;
reg read_data;
wire period_en, pulse_width_en; //写使能
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0)
begin
period<=32'h 00000000;
pulse_width<=32'h 00000000;
end
else begin
if (period_en) period<=write_data;
else period<=period;
if (pulse_width_en) pulse_width<=write_data;
else pulse_width<=pulse_width;
end
end
// period和pulse_width寄存器的读访问
always @(addr or period or pulse_width)
if (addr == 0) read_data=period;
else read_data=pulse_width;
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0) counter<=0;
else if (counter>=period-1) counter<=0;
else counter<=counter+1;
end
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0) off<=0;
else if (counter>=pulse_width) off <= 1;
else if (counter==0) off<=0;
else off<=off;
end
assign period_en = cs & !write_n & !addr;
assign pulse_width_en = cs & !write_n & addr;
endmodule 版主能不能加一下我好友，想请教一下问题ＱＱ３２９２８２３２０谢谢 谢谢LZ我算是学习了 谢谢LZ 好好学习 谢谢楼主！ 谢谢楼主分享！ XIEXIE!!!!!!!!!!!!! 学习了，谢谢楼主！ 谢谢楼主！ 谢分享拉了拉
页:
[1]
2
