分享等精度测频源程序
分享等精度测频源程序本人是初学者,刚接触VHDL不久,仿照书上实例编了频率计程序,下载到MAX7128CPLD后能很好实现 module pwm (clk, write_data, cs, write_n, addr, clr_n, read_data, pwm_out);
input clk;
input write_data;
input cs;
input write_n;
input addr;
input clr_n;
output read_data;
output pwm_out;
定义period和pulse_width寄存器的内容
reg period;
reg pulse_width;
reg counter;
reg off;
reg read_data;
wire period_en, pulse_width_en; 写使能
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0)
begin
period=32'h 00000000;
pulse_width=32'h 00000000;
end
else begin
if (period_en) period=write_data;
else period=period;
if (pulse_width_en) pulse_width=write_data;
else pulse_width=pulse_width;
end
end
period和pulse_width寄存器的读访问
always @(addr or period or pulse_width)
if (addr == 0) read_data=period;
else read_data=pulse_width;
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0) counter=0;
else if (counter=period-1) counter=0;
else counter=counter+1;
end
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0) off=0;
else if (counter=pulse_width) off = 1;
else if (counter==0) off=0;
else off=off;
end
assign period_en = cs & !write_n & !addr;
assign pulse_width_en = cs & !write_n & addr;
endmodule 666666666666666
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