zlsopc 发表于 2010-5-22 11:17:55

RS-232 串口问题

// RS-232 TX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006

//`define DEBUG   // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)

module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input TxD_data;
output TxD, TxD_busy;

parameter ClkFrequency = 25000000;        // 25MHz
parameter Baud = 9600;//115200;
parameter RegisterInputData = 1;        // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted

// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg BaudGeneratorAcc;
`ifdef DEBUG
wire BaudGeneratorInc = 17'h10000;
`else
wire BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
`endif

wire BaudTick = BaudGeneratorAcc;
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc + BaudGeneratorInc;

// Transmitter state machine
reg state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;

reg TxD_dataReg;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;
wire TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;

always @(posedge clk)
case(state)
        4'b0000: if(TxD_start)state <= 4'b0001;
        4'b0001: if(BaudTick) state <= 4'b0100;
        4'b0100: if(BaudTick) state <= 4'b1000;// start
        4'b1000: if(BaudTick) state <= 4'b1001;// bit 0
        4'b1001: if(BaudTick) state <= 4'b1010;// bit 1
        4'b1010: if(BaudTick) state <= 4'b1011;// bit 2
        4'b1011: if(BaudTick) state <= 4'b1100;// bit 3
        4'b1100: if(BaudTick) state <= 4'b1101;// bit 4
        4'b1101: if(BaudTick) state <= 4'b1110;// bit 5
        4'b1110: if(BaudTick) state <= 4'b1111;// bit 6
        4'b1111: if(BaudTick) state <= 4'b0010;// bit 7
        4'b0010: if(BaudTick) state <= 4'b0011;// stop1
        4'b0011: if(BaudTick) state <= 4'b0000;// stop2
        default: if(BaudTick) state <= 4'b0000;
endcase

// Output mux
reg muxbit;
always @( * )
case(state)
        3'd0: muxbit <= TxD_dataD;
        3'd1: muxbit <= TxD_dataD;
        3'd2: muxbit <= TxD_dataD;
        3'd3: muxbit <= TxD_dataD;
        3'd4: muxbit <= TxD_dataD;
        3'd5: muxbit <= TxD_dataD;
        3'd6: muxbit <= TxD_dataD;
        3'd7: muxbit <= TxD_dataD;
endcase

// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state & muxbit);// register the output to make it glitch free

endmodule

其中的
TxD <= (state<4) | (state & muxbit);
是什么意思?它能实现发送起始位0和两位停止位吗?

fpgaw 发表于 2010-5-23 06:56:28

RS-232发送模块方案下载
http://www.fpgaw.com/viewthread.php?tid=213&highlight=RS-232

weibode01 发表于 2010-11-9 11:09:43

这个方案好、、、、

wushimin6 发表于 2011-8-31 15:54:56

:victory::victory::victory:

583292374 发表于 2011-8-31 16:49:28

看的不是很懂！谢谢你的分享！

liujilei311 发表于 2011-9-1 07:45:00

恩，这个方案是不错！！！！！
页: [1]
查看完整版本: RS-232 串口问题