Senior FPGA Designer 杭州依赛通信有限公司
发布日期： 2010-05-24 工作地点： 杭州 招聘人数： 若干工作年限： 五年以上 语言要求： 英语 熟练
职位描述
Major Responsibilities:
Key contributor to the logic design team, responsible for developing FPGAs, ASICs and digital hardware for advanced communications products.
Perform the following aspects of FPGA and ASIC design: regular interaction with other engineers, requirements analysis, specification, architecture, coding, test bench design, verification, synthesis, FPGA place and route and ASIC release.
Working in a project team, work closely with software developers.
Qualifications:
BSEE/CS, or equivalent;
5+ years’ relevant technical experience in hardware design;
Experienced with FPGA design using VHDL with packet processing:
Positive can-do disposition;
Strong work ethic;
Results-oriented problem-solver who requires minimal supervision
Ability to work in a team environment are required
Excellent reading and good written communication skills in English.
Preferences:
Knowledge of low power design techniques utilizing multiple clock domains and gated clocks is a plus
Experience with converting FPGA designs to ASICs is a plus.
Good verbal communication skill in English is a plus.
联系方式
电子邮箱： job.ecichina@ecitele.com
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