这是一个基于FPGA的电子万年历设计，哪个高手进来帮下忙
用Xilinx ISE Design Suite 13.2， Verilog HDL语言 Nexys3开发板。现在只实现了电子钟的功能，怎么加年月日和小时啊module main(clk,sw,an,seg,second_0,second_1,minute_0,minute_1 );input clk;
input sw;
outputan;
outputseg;
output second_0;
outputsecond_1;
output minute_0;
outputminute_1;
reg an;
reg seg;
regsecond_0;
regsecond_1;
regminute_0;
regminute_1;
regcnt;
reg a,b,c,d;
reg temp;
reg second_t_1;
reg minute_t_0;
reg minute_t_1;
initial
begin
a=0;
temp=2'b0;
second_0=31'b0;
second_1=4'b0;
minute_0=4'b0;
minute_1=4'b0;
end
always@(posedge clk)
begin
if(cnt==1'b1)
cnt<=21'b0;
else
cnt<=cnt+1'b1;
end
always@(posedge clk)
begin
if(sw!=2'b1)
begin
if(second_0>=4'b1010)
second_0<=31'b0;
else
second_0<=second_0+1'b1;
end
else
begin
if(sw==2'b0)
second_0<=sw;
else
second_0<=second_0;
end
end
always@(posedge clk)
begin
if(sw!=2'b1)
begin
if(second_0==4'b1010)
second_1<=second_1+1'b1;
if(second_1>=4'b0110)
second_1<=4'b0;
end
else
begin
if(sw==2'b1)
second_1<=sw;
end
end
always@(posedge clk)
begin
if(sw!=2'b1)
begin
if(second_1==4'b0110)
minute_0<=minute_0+1'b1;
if(minute_0>=4'b1010)
minute_0<=4'b0000;
end
else
begin
if(sw==2'b10)
minute_0<=sw;
end
end
always@(posedge clk)
begin
if(sw!=2'b1)
begin
if(minute_0==4'b1010)
minute_1<=minute_1+1'b1;
if(minute_1>=4'b0110)
minute_1<=4'b0000;
end
else
begin
if(sw==2'b11)
minute_1<=sw;
end
end
always@(posedge clk)
begin
case(sw)
2'b00:
begin
if(second_1==second_t_1)
a<=1;
else
a<=0;
if(minute_0==minute_t_0)
b<=1;
else
b<=0;
if(minute_1==minute_t_1)
c<=1;
else
c<=0;
d<=a&b&c;
if(cnt==4'b0)
begin
if(sw!=1||d!=1)
case(second_0)
4'b0:begin seg<=8'b11000000;end
4'b1:begin seg<=8'b11111001;end
4'b10:begin seg<=8'b10100100;end
4'b11:begin seg<=8'b10110000;end
4'b100:begin seg<=8'b10011001;end
4'b101:begin seg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:begin seg<=8'b11111000;end
4'b1000:begin seg<=8'b10000000;end
4'b1001:begin seg<=8'b10010000;end
endcase
else
seg<=8'b11111110;
an<=4'b1110;
end
if(cnt==4'b01)
begin
if(sw!=1||d!=1)
case(second_1)
4'b0:beginseg<=8'b11000000;end
4'b1:beginseg<=8'b11111001;end
4'b10:beginseg<=8'b10100100;end
4'b11:beginseg<=8'b10110000;end
4'b100:beginseg<=8'b10011001;end
4'b101:beginseg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:beginseg<=8'b11111000; end
4'b1000:begin seg<=8'b10000000;end
4'b1001:beginseg<=8'b10010000;end
endcase
else
seg<=8'b11110111;
an<=4'b1101;
end
if(cnt==4'b10)
begin
if(sw!=1||d!=1)
case(minute_0)
4'b0: beginseg<=8'b11000000;end
4'b1: beginseg<=8'b11111001;end
4'b10:beginseg<=8'b10100100;end
4'b11:beginseg<=8'b10110000;end
4'b100: beginseg<=8'b10011001;end
4'b101: beginseg<=8'b10010010;end
4'b110: begin seg<=8'b10000010;end
4'b111:beginseg<=8'b11111000; end
4'b1000:begin seg<=8'b10000000;end
4'b1001:beginseg<=8'b10010000;end
endcase
else
seg<=8'b11110111;
an<=4'b1011;
end
if(cnt==4'b11)
begin
if(sw!=1||d!=1)
case(minute_1)
4'b0:beginseg<=8'b11000000;end
4'b1:beginseg<=8'b11111001;end
4'b10:beginseg<=8'b10100100;end
4'b11:beginseg<=8'b10110000;end
4'b100:beginseg<=8'b10011001;end
4'b101:beginseg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:beginseg<=8'b11111000; end
4'b1000:begin seg<=8'b10000000;end
4'b1001:beginseg<=8'b10010000;end
endcase
else
seg<=8'b11111110;
an<=4'b0111;
end
end
2'b1:begin//2
temp<=sw;
case(temp)
2'b0: begin //0
an<=4'b1110;
seg<=8'b10000001;
case(second_0)
4'b0:begin seg<=8'b11000000;end
4'b1:begin seg<=8'b11111001;end
4'b10:begin seg<=8'b10100100;end
4'b11:begin seg<=8'b10110000;end
4'b100:begin seg<=8'b10011001;end
4'b101:begin seg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:begin seg<=8'b11111000;end
4'b1000:begin seg<=8'b10000000;end
4'b1001:begin seg<=8'b10010000;end
endcase
end//0
2'b1: begin
an<=4'b1101;
seg<=8'b10000001;
case(second_1)
4'b0:begin seg<=8'b11000000;end
4'b1:begin seg<=8'b11111001;end
4'b10:begin seg<=8'b10100100;end
4'b11:begin seg<=8'b10110000;end
4'b100:begin seg<=8'b10011001;end
4'b101:begin seg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:begin seg<=8'b11111000;end
4'b1000:begin seg<=8'b10000000;end
4'b1001:begin seg<=8'b10010000;end
endcase
end
2'b10:begin
//if(sw==1) minute_0<=sw;
an<=4'b1011;
seg<=8'b10000001;
case(minute_0)
4'b0:begin seg<=8'b11000000;end
4'b1:begin seg<=8'b11111001;end
4'b10:begin seg<=8'b10100100;end
4'b11:begin seg<=8'b10110000;end
4'b100:begin seg<=8'b10011001;end
4'b101:begin seg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:begin seg<=8'b11111000;end
4'b1000:begin seg<=8'b10000000;end
4'b1001:begin seg<=8'b10010000;end
endcase
end
2'b11:begin
an<=4'b0111;
seg<=8'b10000001;
case(minute_1)
4'b0:begin seg<=8'b11000000;end
4'b1:begin seg<=8'b11111001;end
4'b10:begin seg<=8'b10100100;end
4'b11:begin seg<=8'b10110000;end
4'b100:begin seg<=8'b10011001;end
4'b101:begin seg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:begin seg<=8'b11111000;end
4'b1000:begin seg<=8'b10000000;end
4'b1001:begin seg<=8'b10010000;end
endcase
end
endcase
end
2'b10:begin
temp<=sw;
case(temp)
2'b0: begin
an<=4'b0000;
seg<=8'b10001001;
end
2'b1:begin
an<=4'b1101;
seg<=8'b10000001;
second_t_1<=sw;
case(second_t_1)
4'b0:begin seg<=8'b11000000;end
4'b1:begin seg<=8'b11111001;end
4'b10:begin seg<=8'b10100100;end
4'b11:begin seg<=8'b10110000;end
4'b100:begin seg<=8'b10011001;end
4'b101:begin seg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:begin seg<=8'b11111000;end
4'b1000:begin seg<=8'b10000000;end
4'b1001:begin seg<=8'b10010000;end
endcase
end
2'b10:begin
an<=4'b1011;
seg<=8'b10000001;
minute_t_0<=sw;
case(minute_t_0)
4'b0:begin seg<=8'b11000000;end
4'b1:begin seg<=8'b11111001;end
4'b10:begin seg<=8'b10100100;end
4'b11:begin seg<=8'b10110000;end
4'b100:begin seg<=8'b10011001;end
4'b101:begin seg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:begin seg<=8'b11111000;end
4'b1000:begin seg<=8'b10000000;end
4'b1001:begin seg<=8'b10010000;end
endcase
end
3'b11:begin
an<=4'b0111;
seg<=8'b10000001;
minute_t_1<=sw;
case(minute_t_1)
4'b0:begin seg<=8'b11000000;end
4'b1:begin seg<=8'b11111001;end
4'b10:begin seg<=8'b10100100;end
4'b11:begin seg<=8'b10110000;end
4'b100:begin seg<=8'b10011001;end
4'b101:begin seg<=8'b10010010;end
4'b110:begin seg<=8'b10000010;end
4'b111:begin seg<=8'b11111000;end
4'b1000:begin seg<=8'b10000000;end
4'b1001:begin seg<=8'b10010000;end
endcase
end
endcase
end //3
endcase
end
endmodule
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