求助，时序仿真结果正确，连上fpga后出问题（nios软核只提供一个输入）
程序的主要功能是给两个输入，将其分别乘查找表中数据，然后输出。下面是我的ip核和接口程序，问题：我将ip核和接口程序连在一起进行时序仿真时输出结果正确（乘法用的是并行乘法器，时钟周期是20ns）但集成到sopc，de2开发板实现，用嵌入式逻辑分析仪观察时（nios2软核就一句话，实现给定两个输入的功能），输出是恒定值。请大神指导一下，万分感谢ip核
`define toni 20 //toni4/m+1
`define tonu 25 //tonu4/m+1
`define toffi 35 //toffi3/m+1
`define toffu 35 //toffu4/m+1
module switching(clk,switches,U0,I0,reset,I,U);
input clk;
input switches;//0:on;1:off;
input wire U0;
input wire I0;
input wire reset;
output regU,I;
wireI1,U1;
regt1=0;
regt2=0;
regt3=0;
regt4=0;
regKI,KU;
reg KIon ;
reg KUon ;
reg KIoff;
reg KUoff;
initial
begin
KIon=16'b0000000000000000;
KIon=16'b0000000000000000;
KIon=16'b0000001010101010;
KIon=16'b0000100000000000;
KIon=16'b0000110101010101;
KIon=16'b0001001010101010;
KIon=16'b0001100000000000;
..........//这是数据表
end
always@(posedge clk)
begin
if(reset==0)
begin
t1=0;
t3=0;
end
if (switches==0)
begin
if (t1<`toni)t1=t1+1;
KI=KIon;
t3=0;
end
else if(switches==1)
begin
if (t3<`toffi)t3=t3+1;
KI=KIoff;
t1=0;
end
end
mul_16 mulI(I0,KI,I1);
always@(posedge clk)
begin
if(reset==0)
begin
t2=0;
t4=0;
end
if (switches==0)
begin
if (t2<`tonu)t2=t2+1;
KU=KUon;
t4=0;
end
else if(switches==1)
begin
if (t4<`toffu)t4=t4+1;
KU=KUoff;
t2=0;
end
end
mul_16 mulU(U0,KU,U1);
always@(posedge clk)
begin
I<={13'b0000000000000,I1};
U<={13'b0000000000000,U1};
end
endmodule
这是接口程序
module Avalon_interface(
clk,
reset_n,
U,
I,
chipselect,
address,
read,
readdata,
write,
writedata,
U0,
I0,
switches,
reset
);
input clk;
input reset_n;
input chipselect;
input address;
input read;
input write;
input writedata;
input U,I;
outputreg reset;
output reg readdata;
output reg U0;
output reg I0;
outputreg switches;//0:on;1:off
reg ui_select,switch_select;
/*
always@(address)
begin
ui_select<=0;
switch_select<=0;
case(address)
1'b0:ui_select<=1;
1'b1:switch_select<=1;
endcase
end
*/
always @ (posedge clk or negedge reset_n)
begin
if(reset_n==1'b0)
begin
U0<=16'b0000000000000000;
I0<=16'b0000000000000000;
switches<=1'b0;
end
else
if(write & chipselect)
begin
U0<=writedata;
I0<={1'b0,writedata};
switches<=writedata;
end
end
/*
always @ (posedge clk or negedge reset_n)
begin
if(reset_n==1'b0)
switches=1'b0;
else
if(write & chipselect & switch_select)
begin
switches<=writedata;
end
end
*/
always @ (read or address or chipselect)
begin
if(read & chipselect)
case(address)
1'b0:readdata<=U;
1'b1:readdata<=I;
default:
begin
readdata<=0;
end
endcase
end
always @ (reset_n)
begin
reset<=reset_n;
end
endmodule
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