双向管脚（clocked bidirectional pin）Verilog代码
基本组合逻辑功能-Verilog HDL 程序举例双向管脚（clocked bidirectional pin）
Verilog HDL: Bidirectional Pin
This example implements a clocked bidirectional pin in Verilog HDL.
The value of OE determines whether bidir is an input, feeding in inp, or a tri-state, driving out the value b.
bidir.v
module bidirec (oe, clk, inp, outp, bidir);
// Port Declaration
inputoe;
inputclk;
input inp;
output outp;
inout bidir;
reg a;
reg b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;
// Always Construct
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule 双向管脚（clocked bidirectional pin）Verilog代码
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