帮小弟看看vrilog程序问题~~~谢谢
module qpsk(clk,rst,dac_clk,dac_data,dac_cs,dac_ldac);input rst, clk;
output dac_data,dac_cs,dac_ldac,dac_clk;
reg dac_data,dac_cs,dac_clk;
reg x;
wire dac_ldac;
reg count;
reg cnt;
reg cnt1;
reg y;
reg y_buf;
reg xreg;//2bit数据组标识
reg xx;
reg yreg;//2bit并行数据
reg shift_reg;
//m序列发生器
always @(posedge dac_clk or negedge rst)
begin
if(!rst)
begin shift_reg<=5'b00001;end //异步复位,低电平有效
else begin
shift_reg<=shift_reg ^ shift_reg;
shift_reg<=shift_reg;
x<=shift_reg;
end
end
always @(posedge dac_clk or negedge rst) //串并转换
begin
if(!rst)
begin
xreg<=2'b0;
yreg<=2'b0;
end
elsebegin
if (count==9'h0)
begin
xreg<=x;
yreg<=xreg;
end
else if (count==9'h100)
begin
xreg<=x;
end end
end
always @(posedge dac_clk or negedge rst)
begin
if(!rst) cnt1<=9'h0;
else
begin
if(cnt1==9'b1)
cnt1<=9'b0;
else
cnt1<=cnt1+1'b1;
end
end
always @(posedge dac_clk or negedge rst) /*选相电路*/
begin
if(!rst) begin count<=0; end
elsebegin
if(cnt1==257)
begin
case(yreg)
2'b11:count<=0; //0
2'b01:count<=128; //π/2
2'b00:count<=256; //π
2'b10:count<=384; //3π/2
default:count<=0;
endcase
end
elsebegin count<=count+1;end
end end
wire jug;
assign jug=(count/16);
always @(posedge dac_clk or negedge rst) /*十六相载波发生电路*/
begin
if(!rst)
begin
y<=16'h0;
end
else
begin
case(jug)
0:y<=16'h7FFF; 1:y<=16'h98F8;
2:y<=16'hB0FB; 3:y<=16'hC71C;
4:y<=16'hDA81; 5:y<=16'hEA6C;
6:y<=16'hF640; 7:y<=16'hFD89;
8:y<=16'hFFFE; 9:y<=16'hFD89;
10:y<=16'hF640; 11:y<=16'hEA6C;
12:y<=16'hDA81; 13:y<=16'hC71C;
14:y<=16'hB0FB; 15:y<=16'h98F8;
16:y<=16'h7FFF; 17:y<=16'h6706;
18:y<=16'h4F03; 19:y<=16'h38E2;
20:y<=16'h257D; 21:y<=16'h1592;
22:y<=16'h09BE; 23:y<=16'h0275;
24:y<=16'h0000; 25:y<=16'h0275;
26:y<=16'h09BE; 27:y<=16'h1592;
28:y<=16'h257D; 29:y<=16'h38E2;
30:y<=16'h4F03; 31:y<=16'h6706;
default:y<=0;
endcase
end
end
always @(posedge dac_clk or negedge rst)
begin
if(!rst)
y_buf<=16'b0;
else
begin
if(count/16==0)
y_buf<=y;
else
y_buf<=(y_buf<<1);
end
end
//DAC控制
reg next;
parameterstate1 =3'd0;
parameterstate2 =3'd1;
parameterstate3 =3'd2;
parameterstate4 =3'd3;
reg count1;
/*产生dac_clk*/
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
count1<=16'd0;
dac_clk<=1'b1;
end
else
if(count1==16'd100)
begin
count1<=16'd0;
dac_clk<=~dac_clk;
end
else count1<=count1+16'b1;
end
/*传输数据*/
reg cnt2;
reg cnt2_en;
wire cnt2_rst;
always @(posedge dac_clk or negedge rst)
begin
if(!rst)
begin
cnt2<=5'b0;
end
else if(cnt2_en)
begin
if(cnt2_rst)
cnt2<=5'b0;
else
cnt2<=cnt2+1'b1;
end
end
assign cnt2_rst=(cnt2==16)?1'b1:1'b0;
always @(posedge dac_clk or negedge rst)
begin
if(!rst)
begin
next<=state1;
dac_cs<=1'b1;
cnt2_en<=1'b0;
end
else
begin
case (next)
state1 :
begin
dac_cs<=1'b0;
next<=state2;
cnt2_en<=1'b0;
end
state2 :
begin
cnt2_en<=1'b1;
dac_data<=y_buf;
next<=state3;
end
state3 :
begin
if(cnt2<17)
next<=state2;
else
begin
next<=state4;
end
end
state4:
begin
dac_cs<=1'b1;
next<=state1;
end
default:next<=state1;
endcase
end
end
assign dac_ldac=1'b0;
endmodule
这是我做的QPSK调制，然后驱动DAC，DAC芯片是DAC8831，但波形出来有问题啊，不知道哪里错了，哪位麻烦给指点一下，谢谢拉
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