上海网诺通讯技术有限公司
职位标签:PCB设计 FPGA CPLD职位职能:高级硬件工程师硬件工程师
职位描述:
工作职责:
1、负责产品硬件原理图和PCB设计和测试
2、合理平衡产品开发时间，质量，成本
技能需求：
必备技能：
1、能熟练使用Cadence concept 和allegro 工具进行原理图和PCB 的设计
2、熟悉Verilog，能进行简单的逻辑设计
3、有单板硬件设计经验
4、能熟练使用数字示波器
5、2年以上硬件相关工作经验或者具备2年硬件开发项目经历
加分技能：
1、有6年以上PCB 单板设计经验
2、有FPGA 或者CPLD 逻辑设计经验
3、很强的沟通能力
教育背景
本科及以上 职位标签:FPGA
职位职能:高级硬件工程师硬件工程师
职位描述:
职位简介：
The FPGA design verification engineer will be the key participant in complex networking FPGA/ASIC development.
工作职责(Responsibilities)：
The verification engineer will participate or own functional spec, write verification plan, build verification environment, write testcase, run simulation (include gate level) and debug the design, be responsible for design quality by achieving certain coverage goal.Required
职位需求(Requirement)：
Experience with Vera or SystemVerilog is a must
Significant verification experience on complex ASICs/FPGAs verification
Knowledge of OOP programming
Experience on random, pseudo-random based verification
Experience on functional coverage
Basic logic design skill (verilog RTL coding, basic design structure) is necessary
Basic knowledge of networking concepts
Desired Skills:
In-depth knowledge of the advanced verification methodologies (such as RVM/VMM/UVM)
Programming using script language (such as unix shell, Perl, Tcl, etc)
Education:
Requires MSEE or BSEE/CS degree equivalent plus significant experience in design verification (3~5 years).
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