元件例化时的端口映射
做了一个小实验，发现一个问题，没想明白，请高人帮忙看看。谢谢！
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY nd2 IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC );
END nd2;
ARCHITECTURE nd2behv OF nd2 IS
BEGIN
c <= a NAND b;
END nd2behv ;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ord41 IS
PORT ( a1, b1, c1, d1 : IN STD_LOGIC;
z1 : OUT STD_LOGIC );
END ord41;
ARCHITECTURE ord41behv OF ord41 IS
COMPONENT nd2
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END COMPONENT;
BEGIN
u1 : nd2 PORT MAP (a=>c1, b=>d1, c =>z1);--运行正确
u2 : nd2 PORT MAP (c1=>a, d1=>b, z1 =>c);--Quartus报错
u3 : nd2 PORT MAP (c1<=a, d1<=b, z1<=c); --Quartus报错
u4 : nd2 PORT MAP (a<=c1, b<=d1, c<=z1); --Quartus报错
END ARCHITECTURE ord41behv; 语法规定的啊，大家都这么写，在这方面钻牛角就不用了吧？<br>
VHDL的语法规定严格，也有好处。
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