状态机的问题
本帖最后由 fpgaw 于 2010-11-19 09:14 编辑library IEEE;
use IEEE.std_logic_1164.all;
entity control is
Port (clk,done,reset,set_time,start_cook,test:in std_logic;
cook,load_8888,load_clk,load_done: out std_logic);
end control;
architecture A of control is
type STATE_TYPE is (idle,lamp_test,set_clock,timer,done_msg);
signal NEXT_STATE,PRESENT_STATE: STATE_TYPE;
begin
process (clk,reset)
begin
if reset='1' then
present_state<=idle;
elsif clk'event and clk='1' then
present_state<=next_state;
end if;
end process;
process (present_state,set_time,start_cook,test,done)
begin
next_state<=idle;
load_8888<='0';
load_done<='0';
load_clk<='0';
cook<='0';
case present_state is
when lamp_test=>
load_8888<='1';
when set_clock=>
load_clk<='1';
when done_msg=>
load_done<='1';
when idle=>
if test='1' then
next_state<=lamp_test;
load_8888<='1';
elsif set_time='1' then
next_state<=set_clock;
load_clk<='1';
elsif start_cook='1' and done='0' then
next_state<=timer;
cook<='1';
end if;
when timer=>
if done='1' then
next_state<=done_msg;
load_done<='1';
else
next_state<=timer;
cook<='1';
end if;
end case;
end process;
end A; 生活啊~~~<br>
就像一坨屎
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