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UFP 发表于 2010-6-26 00:19:49

verilog状态机死机

本帖最后由 fpgaw 于 2010-11-19 06:37 编辑

--状态转换---
process(LCLK1)
begin
if LCLK1'event and LCLK1='1' then
sdram_current<=sdram_next;
end if;
end process;
----状态机逻辑---
process(ADS,LHOLD,LWDRD,ADDR_MSB,LBE)
begin
case sdram_current is
----------
when st0=> ready<='1';sdram_en<='0';
if (ADS='0' and LHOLD='1') then
ADDR_MSB(11 downto 0)<=LA(21 downto 10);
sdram_next<=st1;
else
sdram_next<=st0;
end if;
----------
when st1=> sdram_en<='0';
if (ADS='1') then
ready<='0';
sdram_next<=st2;
else
ready<='1';
sdram_next<=st1;--ADS=0
end if;
-----------
when st2=> sdram_en<='0';
if (ADDR_MSB(11 downto 0)="000000000011" and LBE(3 downto 0)="1111") then
sdram_addr(7 downto 0)<=LA(9 downto 2);
sdram_next<=st3;--valid address
else
sdram_addr(7 downto 0)<=sdram_addr(7 downto 0);
sdram_next<=st0;--invalid address
end if;
-----------
when st3=> ready<='0';
if(LWDRD='1') then
sdram_we<='1';--write data
elsif(LWDRD='0') then
sdram_we<='0';--read data
end if;
sdram_next<=st4;
------------
when st4=> ready<='0';
sdram_en<='1'; ---enable sdram chip select
sdram_next<=st5;
------------
when st5=> ready<='1';
sdram_en<='0';
sdram_next<=st0;--finish one time operation
------------
when others=> ready<='1';
sdram_en<='0';
sdram_next<=st0;
------------
end case;
end process;

longtim 发表于 2010-6-26 01:50:49

本帖最后由 fpgaw 于 2010-7-3 06:12 编辑

以上是我的VHDL代码，请各位路过的帮忙看看，解决问题给你们加分<br>
我用MODELSIM6.1F仿真，发现状态机进入ST2状态就停止了，我看了好久都没发现是那儿错了。<br>
不管运行多久，状态机就是停在ST2不动....很郁闷<br>
高手请帮忙..............
        [

usd 发表于 2010-6-26 03:41:28

我学了不久，可能没有指到点子上，望见谅！<br>
<br>
<br>
<br>
--状态转换---<br>
process(LCLK1)&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; --这个进程中是否应该设置状态机的初始值st0？<br>
begin<br>
&nbsp;&nbsp;if LCLK1'event and LCLK1='1' then<br>
&nbsp; &nbsp; sdram_current&lt;=sdram_next;<br>
&nbsp;&nbsp;end if;<br>
end process;<br>
<br>
----状态机逻辑---<br>
process(ADS,LHOLD,LWDRD,ADDR_MSB,LBE)&nbsp; &nbsp;&nbsp; &nbsp;--敏感信号表中是否应该包含sdram_current？<br>
begin<br>
case sdram_current is<br>
----------<br>
when st0=&gt; ready&lt;='1';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;sdram_en&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;if (ADS='0' and LHOLD='1') then&nbsp;&nbsp;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;ADDR_MSB(11 downto 0)&lt;=LA(21 downto 10);<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_next&lt;=st1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;else<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_next&lt;=st0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end if;<br>
----------&nbsp; &nbsp;<br>
when st1=&gt; sdram_en&lt;='0';&nbsp; &nbsp;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;if (ADS='1') then<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;ready&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_next&lt;=st2;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;else<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;ready&lt;='1';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_next&lt;=st1;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;--ADS=0<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end if;<br>
-----------<br>
when st2=&gt; sdram_en&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;if (ADDR_MSB(11 downto 0)="000000000011" and LBE(3 downto 0)="1111") then<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_addr(7 downto 0)&lt;=LA(9 downto 2);<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_next&lt;=st3;--valid address<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;else<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_addr(7 downto 0)&lt;=sdram_addr(7 downto 0);<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_next&lt;=st0;--invalid address<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end if;<br>
-----------<br>
when st3=&gt; ready&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;if(LWDRD='1') then<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_we&lt;='1';&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;--write data<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;elsif(LWDRD='0') then<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_we&lt;='0';--read data<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end if;<br>
sdram_next&lt;=st4;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;--这条语句为什么要放在这里？游离于case语句之外了？<br>
------------<br>
when st4=&gt; ready&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;sdram_en&lt;='1';&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;---enable sdram chip select<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;sdram_next&lt;=st5;<br>
------------<br>
when st5=&gt; ready&lt;='1';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;sdram_en&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;sdram_next&lt;=st0;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;--finish one time operation<br>
------------<br>
when others=&gt; ready&lt;='1';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_en&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;sdram_next&lt;=st0;&nbsp;&nbsp;<br>
------------<br>
end case;<br>
end process;

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