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CHAN 发表于 2010-6-26 00:34:26

状态机无任何输出高手进

我的代码：

moduleabc (
 clk_c,rst_c,
 wr_c,re_c,
 dataout_c,datain_c,add_c,
 flash_sel,sram_sel,ram_sel,
 add,data,
 ce_sn,ce_fn,ce_rn,oe_n,we_n,
 lb_n,ub_n,
 out_null
 );
inputclk_c,rst_c;
inputout_null;
inputwr_c,re_c;
inputadd_c;
inputdatain_c;
inputflash_sel,sram_sel,ram_sel;
outputdataout_c;
outputadd;
outputce_sn,ce_fn,ce_rn;
outputoe_n,we_n;
outputlb_n,ub_n;
inoutdata;
wireclk_c,rst_c;
wireout_null;
wirewr_c,re_c;
wireadd_c;
wiredatain_c;
regdataout_c;
regadd;
regce_sn,ce_fn,ce_rn;
regoe_n,we_n;
reglb_n,ub_n;
///////////////////////////////内部信号///////////////////////////////
regCS,NS;
parameterIDLE = 6'b000000,
 WRITE_SRAM = 6'b000001,
 READ_SRAM = 6'b000010,
 WRITE_FLASH = 6'b000100,
 READ_FLASH = 6'b001000,
 WRITE_RAM = 6'b010000,
 READ_RAM = 6'b100000;

regtemp_data;
assigndata = (~wr_c) ? temp_data : 16'bzzzzzzzzzzzzzzzz;
////////////////1st always block, sequential state transition////////////////
always @ (posedge clk_c or negedge rst_c)
begin
if (!rst_c)
CS <= IDLE;
else
CS <=NS;
end
////////////////2nd always block, combinational condition judgment
always @ (rst_c or CS or flash_sel or sram_sel or ram_sel or wr_c or re_c)
begin
NS = 6'bxxxxxx;
case (CS)
IDLE: begin
if((sram_sel) && (~wr_c) && (re_c)) NS = WRITE_SRAM;
else if ((sram_sel) && (wr_c) && (~re_c)) NS = READ_SRAM;
else if ((flash_sel) && (~wr_c) && (re_c)) NS = WRITE_FLASH;
else if ((flash_sel) && (wr_c) && (~re_c)) NS = READ_FLASH;
else if ((ram_sel) && (~wr_c) && (re_c))NS = WRITE_RAM;
else if ((ram_sel) && (wr_c) && (~re_c))NS = READ_RAM;
elseNS = IDLE;
end
WRITE_SRAM: begin
if((sram_sel) && (~wr_c) && (re_c)) NS = WRITE_SRAM;
else if ((sram_sel) && (wr_c) && (~re_c)) NS = READ_SRAM;
else if ((flash_sel) && (~wr_c) && (re_c)) NS = WRITE_FLASH;
else if ((flash_sel) && (wr_c) && (~re_c)) NS = READ_FLASH;
else if ((ram_sel) && (~wr_c) && (re_c))NS = WRITE_RAM;
else if ((ram_sel) && (wr_c) && (~re_c))NS = READ_RAM;
elseNS = IDLE;
end
READ_SRAM: begin
if((sram_sel) && (~wr_c) && (re_c)) NS = WRITE_SRAM;
else if ((sram_sel) && (wr_c) && (~re_c)) NS = READ_SRAM;
else if ((flash_sel) && (~wr_c) && (re_c)) NS = WRITE_FLASH;
else if ((flash_sel) && (wr_c) && (~re_c)) NS = READ_FLASH;
else if ((ram_sel) && (~wr_c) && (re_c))NS = WRITE_RAM;
else if ((ram_sel) && (wr_c) && (~re_c))NS = READ_RAM;
elseNS = IDLE;
end
WRITE_FLASH: begin
if((sram_sel) && (~wr_c) && (re_c)) NS = WRITE_SRAM;
else if ((sram_sel) && (wr_c) && (~re_c)) NS = READ_SRAM;
else if ((flash_sel) && (~wr_c) && (re_c)) NS = WRITE_FLASH;
else if ((flash_sel) && (wr_c) && (~re_c)) NS = READ_FLASH;
else if ((ram_sel) && (~wr_c) && (re_c))NS = WRITE_RAM;
else if ((ram_sel) && (wr_c) && (~re_c))NS = READ_RAM;
elseNS = IDLE;
end
READ_FLASH: begin
if((sram_sel) && (~wr_c) && (re_c)) NS = WRITE_SRAM;
else if ((sram_sel) && (wr_c) && (~re_c)) NS = READ_SRAM;
else if ((flash_sel) && (~wr_c) && (re_c)) NS = WRITE_FLASH;
else if ((flash_sel) && (wr_c) && (~re_c)) NS = READ_FLASH;
else if ((ram_sel) && (~wr_c) && (re_c))NS = WRITE_RAM;
else if ((ram_sel) && (wr_c) && (~re_c))NS = READ_RAM;
elseNS = IDLE;
end
WRITE_RAM: begin
if((sram_sel) && (~wr_c) && (re_c)) NS = WRITE_SRAM;
else if ((sram_sel) && (wr_c) && (~re_c)) NS = READ_SRAM;
else if ((flash_sel) && (~wr_c) && (re_c)) NS = WRITE_FLASH;
else if ((flash_sel) && (wr_c) && (~re_c)) NS = READ_FLASH;
else if ((ram_sel) && (~wr_c) && (re_c))NS = WRITE_RAM;
else if ((ram_sel) && (wr_c) && (~re_c))NS = READ_RAM;
elseNS = IDLE;
end
READ_RAM: begin
if((sram_sel) && (~wr_c) && (re_c)) NS = WRITE_SRAM;
else if ((sram_sel) && (wr_c) && (~re_c)) NS = READ_SRAM;
else if ((flash_sel) && (~wr_c) && (re_c)) NS = WRITE_FLASH;
else if ((flash_sel) && (wr_c) && (~re_c)) NS = READ_FLASH;
else if ((ram_sel) && (~wr_c) && (re_c))NS = WRITE_RAM;
else if ((ram_sel) && (wr_c) && (~re_c))NS = READ_RAM;
elseNS = IDLE;
end
default:
NS = IDLE;
endcase
end
//////////////////////////3rd always block, the sequential FSM output////////////////////////
always @ (posedge clk_c or negedge rst_c)
begin
if (!rst_c)begin
{lb_n,ub_n} <= 2'b11;
{we_n,oe_n} <= 2'b11;
{ce_sn,ce_fn,ce_rn} <= 3'b111;
add <= 17'b0;
dataout_c <= 16'b0;
end
elsebegin
{lb_n,ub_n} <= 2'b11;
{we_n,oe_n} <= 2'b11;
{ce_sn,ce_fn,ce_rn} <= 3'b111;
add <= 17'b0;
dataout_c <= 16'b0;

case (NS)
IDLE: begin
{lb_n,ub_n} <= 2'b11;
{we_n,oe_n} <= 2'b11;
{ce_sn,ce_fn,ce_rn} <= 3'b111;
add <= 17'b0;
dataout_c <= 16'b0;
end
WRITE_SRAM: begin
{lb_n,ub_n} <= 2'b00;
{we_n,oe_n} <= 2'b01;
{ce_sn,ce_fn,ce_rn} <= 3'b011;
add <= add_c;
dataout_c <= 16'b0;
temp_data <= datain_c;
end
READ_SRAM: begin
{lb_n,ub_n} <= 2'b00;
{we_n,oe_n} <= 2'b10;
{ce_sn,ce_fn,ce_rn} <= 3'b011;
add <= add_c;
dataout_c <= data;
end
WRITE_FLASH: begin
{lb_n,ub_n} <= 2'b11;
{we_n,oe_n} <= 2'b01;
{ce_sn,ce_fn,ce_rn} <= 3'b101;
add <= add_c;
dataout_c <= 16'b0;
temp_data <= datain_c;
end
READ_FLASH: begin
{lb_n,ub_n} <= 2'b11;
{we_n,oe_n} <= 2'b10;
{ce_sn,ce_fn,ce_rn} <= 3'b101;
add <= add_c;
dataout_c <= data;
end
WRITE_RAM:begin
{lb_n,ub_n} <= 2'b11;
{we_n,oe_n} <= 2'b01;
{ce_sn,ce_fn,ce_rn} <= 3'b110;
add <= add_c;
dataout_c <= 16'b0;
temp_data <= datain_c;
end
READ_RAM:begin
{lb_n,ub_n} <= 2'b11;
{we_n,oe_n} <= 2'b10;
{ce_sn,ce_fn,ce_rn} <= 3'b110;
add <= add_c;
dataout_c <= data;
end
endcase
end
end
endmodule

Quartus2 综合的结果：见附件

为什么状态机没有任何输出呢？？？望高人指点。

usb 发表于 2010-6-26 02:34:14

你用时钟沿去采样当前状态，输出结果，不能给初值的（复位信号无效时），组合电路才这样使用

interige 发表于 2010-6-26 02:36:18

你是说把第三个always中的else后面的 
 
      {lb_n,ub_n} <= 2'b11; 
      {we_n,oe_n} <= 2'b11; 
      {ce_sn,ce_fn,ce_rn} <= 3'b111; 
      add <= 17'b0; 
      dataout_c <= 16'b0; 
 
去掉吧。好象还是不行喔：（

CCIE 发表于 2010-6-26 02:56:02

buzhidao a  aaaaaaaaaaa

UFP 发表于 2010-6-26 03:55:19

把时序电路里的状态换成当前态（CS）试试！

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状态机无任何输出 高手进

状态机无任何输出高手进