library ieee;<br>
use ieee.std_logic_1164.all;<br>
use ieee.std_logic_unsigned.all;<br>
use ieee.std_logic_arith.all;<br>
entity shaomiao is<br>
generic(size:integer:=4);<br>
port(d0,d1,d2,d3:in std_logic_vector(3 downto 0);<br>
clk:in std_logic;<br>
dout: out std_logic_vector(6 downto 0);<br>
cs: inout std_logic_vector(size-1 downto 0));<br>
end shaomiao;<br>
architecture behavior of shaomiao is<br>
type state is (s0,s1,s2,s3);<br>
signal prestate,nexstate:state;<br>
signal A:std_logic_vector(3 downto 0);<br>
begin<br>
process(clk)<br>
begin<br>
if(clk'event and clk='1')then<br>
prestate<=nexstate; <br>
end if;<br>
end process;<br>
process(prestate)<br>
begin<br>
case prestate is<br>
when s0=>nexstate<=s1;<br>
when s1=>nexstate<=s2;<br>
when s2=>nexstate<=s3;<br>
when others=>nexstate<=s0;<br>
end case;<br>
end process;<br>
process(prestate)<br>
begin<br>
case prestate is<br>
when s0=>A<=d0;cs<="0111";<br>
when s1=>A<=d1;cs<="1011";<br>
when s2=>A<=d2;cs<="1101";<br>
when others=>A<=d3;cs<="1110";<br>
end case;<br>
end process;<br>
process(A)<br>
begin<br>
case A is<br>
when"0000"=>dout<="1111110";<br>
when"0001"=>dout<="0110000";<br>
when"0010"=>dout<="1101101";<br>
when"0011"=>dout<="1111001";<br>
when"0100"=>dout<="0110011";<br>
when"0101"=>dout<="1011011";<br>
when"0110"=>dout<="0011111";<br>
when"0111"=>dout<="1110000";<br>
when"1000"=>dout<="1111111";<br>
when"1001"=>dout<="1111011";<br>
when others =>dout<="0000000";<br>
end case;<br>
end process;<br>
end behavior; 还不错<br>
<br>
我的程序都没人帮我弄 不错<br>
http://bbs.vibesic.com/images/smilies/default/biggrin.gif 你可以看一下标号是SHOW的这个进程,我没空写,这是我以前坐的!<br>
LIBRARY IEEE;<br>
USE IEEE.STD_LOGIC_1164.ALL;<br>
USE IEEE.STD_LOGIC_UNSIGNED.ALL;<br>
ENTITY JSXS IS<br>
PORT(CLR,CLK,EN: STD_LOGIC;<br>
SEL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);<br>
LED8D: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));<br>
END ENTITY JSXS;<br>
ARCHITECTURE ART OF JSXS IS<br>
SIGNAL CLK1S: STD_LOGIC;<br>
SIGNAL D3,D2,D1,D0: STD_LOGIC_VECTOR(3 DOWNTO 0);<br>
SIGNAL D: STD_LOGIC_VECTOR(3 DOWNTO 0);<br>
BEGIN<br>
CLKDIV1S
http://bbs.vibesic.com/images/smilies/default/tongue.gif
ROCESS(CLR,CLK)<br>
VARIABLE NCLK: STD_LOGIC;<br>
VARIABLE CNT: INTEGER RANGE 0 TO 249999;<br>
BEGIN<br>
IF CLR='1' THEN<br>
CNT:=0;<br>
NCLK:='0';<br>
ELSIF CLK'EVENT AND CLK='1' THEN<br>
IF CNT=249999 THEN<br>
CNT:=0;<br>
NCLK:='1';<br>
ELSE<br>
CNT:=CNT+1;<br>
NCLK:='0';<br>
END IF;<br>
END IF;<br>
CLK1S<=NCLK;<br>
END PROCESS CLKDIV1S;<br>
CNT3600
http://bbs.vibesic.com/images/smilies/default/tongue.gif
ROCESS(CLR,EN,CLK1S)<br>
VARIABLE Q3,Q2,Q1,Q0: STD_LOGIC_VECTOR(3 DOWNTO 0);<br>
BEGIN<br>
IF CLR='1' THEN<br>
Q3:="0000";<br>
Q2:="0000";<br>
Q1:="0000";<br>
Q0:="0000";<br>
ELSIF CLK1S'EVENT AND CLK1S='1' THEN<br>
IF EN='1' THEN<br>
IF Q0="1001" THEN<br>
Q0:="0000";<br>
IF Q1="0101" THEN<br>
Q1:="0000";<br>
IF Q2="1001" THEN<br>
Q2:="0000";<br>
IF Q3="0101" THEN<br>
Q3:="0000";<br>
ELSE <br>
Q3:=Q3+1;<br>
END IF;<br>
ELSE<br>
Q2:=Q2+1;<br>
END IF;<br>
ELSE<br>
Q1:=Q1+1;<br>
END IF;<br>
ELSE<br>
Q0:=Q0+1;<br>
END IF;<br>
END IF;<br>
END IF;<br>
D3<=Q3;<br>
D2<=Q2;<br>
D1<=Q1;<br>
D0<=Q0;<br>
END PROCESS CNT3600;<br>
SHOW
http://bbs.vibesic.com/images/smilies/default/tongue.gif
ROCESS(CLK,D3,D2,D1,D0)<br>
VARIABLE CNT: INTEGER RANGE 0 TO 3;<br>
VARIABLE Q: STD_LOGIC_VECTOR(3 DOWNTO 0);<br>
VARIABLE WEI: STD_LOGIC_VECTOR(3 DOWNTO 0);<br>
BEGIN<br>
IF CLK'EVENT AND CLK='1' THEN<br>
CNT:=CNT+1;<br>
CASE CNT IS<br>
WHEN 0=>WEI:="1110";Q:=D0;<br>
WHEN 1=>WEI:="1101";Q:=D1;<br>
WHEN 2=>WEI:="1011";Q:=D2;<br>
WHEN 3=>WEI:="0111";Q:=D3;<br>
END CASE;<br>
END IF;<br>
D<=Q;<br>
SEL<=WEI;<br>
END PROCESS SHOW;<br>
YM:PROCESS(D)<br>
BEGIN<br>
CASE D IS<br>
WHEN "0000"=>LED8D<="11111100";<br>
WHEN "0001"=>LED8D<="01100000";<br>
WHEN "0010"=>LED8D<="11011010";<br>
WHEN "0011"=>LED8D<="11110010";<br>
WHEN "0100"=>LED8D<="01100110";<br>
WHEN "0101"=>LED8D<="10110110";<br>
WHEN "0110"=>LED8D<="10111110";<br>
WHEN "0111"=>LED8D<="11100000";<br>
WHEN "1000"=>LED8D<="11111110";<br>
WHEN "1001"=>LED8D<="11110110";<br>
WHEN OTHERS=>NULL;<br>
END CASE;<br>
END PROCESS YM;<br>
END ARCHITECTURE ART 保留着以后用
页:
1
[2]