R&D FPGA Design Engineer 00004139--爱立信中国-中国研发总院
发布日期： 2010-04-09 工作地点： 北京 招聘人数： 若干工作年限： 三年以上 语言要求： 英语 熟练 学 历： 硕士
职位描述
Description
To carry out the assigned tasks and report progress to the R&D Head and project manager.
To support the R&D or HW manager in the task to ensure that the HW design activities fulfill the needs within the R&D Center in an efficient way.
HDL logic design and verification.
Qualifications
Master degree in CS, EE, Telecom or equivalent.
Excellent knowledge of Communication systems and their design.
Minimum 5 years experience in HDL logic design and verification.
Minimum 4 years experience in a relevant technical areas; e.g. Transmission networks (SDH, EoS, Metro Ethernet MEF etc), Access technologies (xDSL, PON, CATV etc) or IP Access Aggregation(Ethernet Switching, Routing, QoS etc), with proven industry experience.
Detailed architectural knowledge of Xilinx and Altera FPGA's.
Good communication skills and social ability.
Teamwork.
Fluent English in reading and writing.
To apply this position, please visit https://ericsson.taleo.net/careersection/2/jobdetail.ftl?lang=en&job=00004139 66666666666666
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