verilog通用型表决器设计
本帖最后由 fpgaw 于 2010-7-12 14:13 编辑LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE QQ IS
Constant SHUJU : INTEGER:=10;
END QQ;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.QQ.ALL;
ENTITY BIAOJUEQI IS
PORT(
AA :BIT_VECTOR( SHUJU DOWNTO 0);
ABCDEFG : OUT STD_LOGIC_VECTOR (0 TO 6);
Y : OUT BIT
);
END BIAOJUEQI;
ARCHITECTURE JUE OF BIAOJUEQI IS
BEGIN
PROCESS(AA)
VARIABLE SUM: INTEGER RANGE 0
TO
(SHUJU+1);
BEGIN
SUM:=0;
FOR I IN 0 TO SHUJU LOOP
IF(AA(I)='1') THEN
SUM:=SUM+1;
END IF;
END LOOP;
IF(SUM>(SHUJU/2)) THEN
Y<='1';
ELSE Y<='0';
END IF;
CASE SUM IS
WHEN 0=>ABCDEFG<="1111110";
WHEN 1=>ABCDEFG<="0110000";
WHEN 2=>ABCDEFG<="1101101";
WHEN 3=>ABCDEFG<="1111001";
WHEN 4=>ABCDEFG<="0110011";
WHEN 5=>ABCDEFG<="1011011";
WHEN 6=>ABCDEFG<="1011111";
WHEN 7=>ABCDEFG<="1110000";
WHEN 8=>ABCDEFG<="1111111";
WHEN OTHERS=>ABCDEFG<="1111011";
END CASE;
END PROCESS;
END ARCHITECTURE JUE; 看看，学些一下 gggggggggggg gggggggggggggggggggg ******************dd hhhhhhjjj vvvvvvvvvvvvvvvv 111111R4GNBGHNSFJN
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