用verilog编写testbench,ModelSim的大牛可否过来指点一下？
用verilog编写testbench,ModelSim的大牛可否过来指点一下？我在用verilog编写testbench的时候，编译通过了，但是给他“Creat Wave”的时候出现了 "No ports found in rs_encoder_testbench" 的错误,不知道是什么原因,我刚接触verilog，写testbench也不是很熟，下面是我写得testbench，大家可否指点一下有什么错误？
`timescale 1ns / 1ps
module rs_encoder_testbench;
reg clock;
reg reset;
reg dvalid;
reg clk_ena;
reg data_in;
wire out_enable;
wire data_out;
rs_encoder example ( .clock (clock)
, .reset(reset)
, .dvalid (dvalid)
, .data_in(data_in)
, .data_out (data_out)
, .out_enable (out_enable)
, .clk_ena(clk_ena)
);
always #1 clock = ~clock;
initial
begin
reset = 0;
clock = 0;
#1 reset = 1;
#1 reset = 0;
#1 dvalid=1;
data_in=10;
#1 clk_ena=1;
#40 data_in=45;
#32 dvalid=0;
#40 $finish;
end
initial $monitor($time,,,,,,,"clock=%d reset=%d,dvalid=%d,clk_ena=%d,data_in=%d,data_out=%d,out_enable=%d",clock,reset,dvalid,clk_ena,data_in,data_out,out_enable);
endmodule
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