VHDL编写的60进制计数器，编译出错。
本帖最后由 fpgaw 于 2010-7-11 11:02 编辑初学vhdl，在某书上看到六十进制计数器程序如下。但编译出错。
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter60 is
port(cp,rd,en:in std_logic;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LD:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CO:OUT STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end counter60;
architecture one of counter60 is
signal qn:std_logic_vector(7 downto 0);
begin
co<='1' when (qn=x"59"and en='1') else'0';
process(cp,rd)
if(rd='0') then --错误提示此处 found illegal use of a statement in a declarative part
qn<=X"00";
elsif(cp'EVENT and cp='1')then
if (ld="00")then qn<=d;
elsif (ld(0)='0')then --ld=10
qn(3 downto 0)<=d(3 downto 0);
elsif (ld(1)='0')then--ld=01
qn(7 downto 4)<=d(7 downto 4);
elsif (en='1')then --ld=11
if (qn(3 downto 0)="1001") then
qn(3 downto 0)<="0000";
if (qn(7 downto 4)="0101") then
qn(7 downto 4)<="0000"
else qn(7 downto 4)<=qn(7 downto 4)+1;
end if;
else qn(3 downto0)<=qn(3 downto 0)+1;
end if;
end if;
end if;
end process;
qlt;=qn
end one; ************************************************************ 不好意思<br>
没钱了
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