encounter 发表于 2010-6-27 23:19:30

哪位高人帮我看看verilog程序

本帖最后由 fpgaw 于 2010-7-7 05:35 编辑

用MAXPLUS编译总是有错误 请高人指点
module yybf
(clk,f_4M,f_4K,f_4,news,qd);
inputclk,f_4M,f_4K,f_4,news;//20MHz
output qd;
wire clk,f_4M,f_4K,f_4,mews;
reg high,mid,low;
rega=3;
reg b=23,c=23;
reg d,fbi;
reg qd=0;
always@(posedge clk)
begin
if(a==7)
   begin
    a<=3;
    f_4M=1;
   end
else
   begin
    a<=a+1;f_4M<=0;
   end
end
always@(posedge f_4M)
begin
if(b==1023)
   begin
    b<=23;f_4K<=1;
   end
else
   begin
    b<=b+1;f_4K<=0;
   end
end
always@(posedge f_4)
begin
case({high,mid,low})
'b000000000011: fbi<=2123;
'b000000000101: fbi<=3089;
'b000000000110: fbi<=3646;
'b000000010000: fbi<=4369;
'b000000100000: fbi<=4786;
'b000000110000: fbi<=5157;
'b000001000000: fbi<=5328;
'b000001010000: fbi<=5640;
'b000001100000: fbi<=5918;
'b000001110000: fbi<=6166;
'b000100000000: fbi<=6280;
'b001000000000: fbi<=6488;
'b001100000000: fbi<=6674;
'b010000000000: fbi<=6759;
'b010100000000: fbi<=6915;
'b000000000000: fbi<=8191;
default: fbi<=8191;
endcase
end
assign news=(d==8191);
always@(posedge f_4M)
begin
   if(news)d<=fbi;
   else d<=d+1;
end
always@(posedge news)
beginqd<=~qd;
end
endmodule

VVIC 发表于 2010-6-28 00:10:03

首先，你求助的时候应该说明你想完成什么功能，最好能说明你的代码逻辑。其次，代码的排列一定要规则，不应该出现always@(posedge news)。最后，maxplus2的warning应该贴出来。<br>
<br>
说点语法不对的，大致扫了一眼。<br>
1. reg&nbsp; &nbsp;&nbsp; &nbsp;a=3;&nbsp; &nbsp;<br>
reg b=23,c=23;&nbsp;&nbsp;赋值显然不可能，又不是c语言，要赋值，用reset<br>
2.always@(posedge&nbsp;&nbsp;f_4M) f_4M就是一个时钟信号。。。这种写法造成了一堆时钟，最后的结果就是被时钟搞死。。。应该是在clk里面电平检测f_4M及类似信号。

HDL 发表于 2010-6-28 01:10:50

http://bbs.vibesic.com/images/smilies/default/biggrin.gif
<br>
the guy upstares is right!<br>
form your program style is very important!
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