interi 发表于 2010-6-28 00:35:20

Quartus 延时电路仿真问题

Quartus 延时电路仿真问题

小弟编了一小程序如下,愿意是想延时3个时钟后a的值赋给b.
可无论我怎么仿真,b始终为0.

哪们帮小北看下哪里出错了.多谢!



module delay(a,b,clk);
input a,clk; output b;
reg count,b;

always @(posedge clk)

   if (!a)count<=0;
   else if (count==3)
   begin count<=0; b<=a; end
   else count<=count+1;
endmodule

usd 发表于 2010-6-28 02:20:34

沉的好快啊

interige 发表于 2010-6-28 03:16:36

定义寄存器时最好说明变量的位数，没有说明的话系统默认为一位（定义的count实际上是一位寄存器，count不能等于3吧，因此只能执行最后一个else吧，a的值时钟不能赋予b），同时不要把输入信号作为复位信号用（你把输入信号a当作复位信号了）；下面这样写能实现你的功能<br>
module&nbsp;&nbsp;delay(rst_n,clk,a,b);<br>
input&nbsp; &nbsp; clk;<br>
input&nbsp; &nbsp; rst_n;&nbsp;&nbsp;//复位信号<br>
input&nbsp; &nbsp; a;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;//输入信号<br>
output&nbsp;&nbsp;b;<br>
reg&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;b;<br>
reg&nbsp;&nbsp;&nbsp;&nbsp;count; //说明计数器的位数为2位<br>
<br>
always&nbsp;&nbsp;@ (posedge clk or negedge rst_n)<br>
begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; if(!rst_n)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;count&nbsp; &nbsp;&lt;= 2'b00;&nbsp;&nbsp;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;b&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&lt;= 1'b0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;end<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; else <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;if(count&nbsp;&nbsp;== 2'b10 )<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;count&nbsp;&nbsp;&lt;= 2'b00;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;b&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&lt;= a;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;else <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;count&nbsp;&nbsp;&lt;= count + 1'b1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;end<br>
end<br>
endmodule

interig 发表于 2010-6-28 05:10:19

恩&nbsp;&nbsp;是的

interig 发表于 2010-6-28 05:28:56

多谢yimaoqian兄<br>
俺学习了
        http://bbs.vibesic.com/images/smilies/default/smile.gif

interig 发表于 2010-6-28 06:14:29

仿真已通过,谢谢楼上两们

HANG 发表于 2010-6-28 06:59:18

yimaoqian老大,俺想在原题的基础上略微改动, rst_n为高2个时钟后, a由0变为1,再过3个时钟后a的值赋给b.不知程序要如何改.<br>
俺刚学verilog, 真心求教!
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