请教VHDL语言的高手
--ZZQ.VHDLIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ZZQ IS
PORT(DATA1: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
LD_8888:IN STD_LOGIC;
LD_CLK: IN STD_LOGIC;
LD_DONE:IN STD_LOGIC;
DATA2:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
LOAD:OUT STD_LOGIC);
END ENTITY ZZQ;
ARCHITECTURE ART OF ZZQ IS
BEGIN
PROCESS(DATA1,LD_8888,LD_CLK,LD_DONE) IS
CONSTANT ALL_8:STD_LOGIC_VECTOR(15 DOWNTO 0):="1000100010001000";
CONSTANT DONE:STD_LOGIC_VECTOR(15 DOWNTO 0):="1010101111001101";
VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
LOAD<=LD_8888 OR LD_DONE OR LD_CLK;
TEMP:=LD_8888 & LD_DONE & LD_CLK;
CASE TEMP IS
WHEN "100" => DATA2<=ALL_8; --LOAD_8888 =1
WHEN "010" => DATA2<=DONE; --LOAD_DONE =1
WHEN "001" => DATA2<=DATA1; --LOAD_CLK=1
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END ARCHITECTURE ART;
结果怎么仿真都不对。 说的具体一点你要做什么 这样没有目标的看是看不出来的 或者把Quatus2给的错误报告放上去 你只是给个程序，不知道你的设计功能，又没有说是仿真结果不对还是不能仿真，大家没法给你分析 同意楼上的的说法!
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