求助：dsp2812与fpga连接问题
本帖最后由 fpgaw 于 2010-7-15 13:26 编辑我用2812与fpga，数据总线地址总线连接在一起
fpga另一个分别带了2个数据总线
但现在发现2812一运行就发热
fpga无问题
下面是fpga的代码，帮忙看看有没有错误
module RDBus(
Rst,
AddressIn,
AddressOut,
Wr28,
Rd28,
Cs28,
XclkOut28,
PageAD,
DataBus28,
DataBusAD,
DataBusECAT,
WrECAT,
RdECAT,
RdAD,
CsAD1,
CsAD2,
CsAD3,
CsECAT
);
input Rst;
input AddressIn;
output AddressOut;
input Wr28;
input Rd28;
input Cs28;
input XclkOut28;
input PageAD;
inout DataBus28;
input DataBusAD;
inout DataBusECAT;
output WrECAT,RdECAT,RdAD;
output CsAD1,CsAD2,CsAD3,CsECAT;
wire DataBus28;
wire DataBusAD;
wire DataBusECAT;
reg DataBusReg;
reg DataBusReg2;
initial
begin
DataBusReg2 = 16'b0;
DataBusReg = 16'b0;
end
assign WrECAT = Wr28;
assign RdECAT = Rd28;
assign RdAD = Rd28;
assign AddressOut = AddressIn;
/*
assign CsAD1 = (!PageAD) || Cs28 || (!AddressIn);
assign CsAD2 = (!PageAD) || Cs28 || (!AddressIn);
assign CsAD3 = (!PageAD) || Cs28 || (!AddressIn);
assign CsECAT = PageAD || Cs28;
*/
assign CsAD2 = Cs28;
assign DataBus28 = !Rd28 ? DataBusReg:16'bz;
assign DataBusECAT = !Wr28 ? DataBusReg2:16'bz;
always@(negedge Rd28)
begin
if(PageAD)
DataBusReg <= DataBusAD;
else
DataBusReg <= DataBusECAT;
end
always@(negedge Wr28)
begin
if(!PageAD)
DataBusReg2 <= DataBus28;
end
endmodule
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