新手请教高手指点程序一点问题
下面我自己写得一个逻辑时序程序，但现在在综合是总有一个问题：@E: CL172 :"H:\CIS_SY~1\cis_system.v":24:13:24:14|Only one always block may assign a given variable sp
我不明白什么意思？ 望高手指点！
我的源程序如下：
module cis_system(clk ,clk0,start,rst,clkop,lock, clk1,sp,tr,r_light);
input clk,start,rst,clk0;
output clk1,clkop,lock;
output sp, tr;
outputr_light;
wireclk0;
parameterpixel_count=1288 ;
parametercolor=1;
parameterhigh_time =30;
parameterlow_time =30;
parameterlight_time=20;
parametervol_ref =150;
parameterspi_width =6;
parameterdelay_time=3;
parameterpreclock = 10;
regduty ;
// regvol_ref_1;
reg clk1;
reg sp;
reg tr;
reg r_light;
regclk_count;
assignclk0 = clkop;
initial begin
//vol_ref_1 = 150;
sp = 0;
tr = 0;
clk_count = 0;
r_light =0;
end
always@( posedge rst or posedge clk0 )
begin
if(rst)
begin
sp=0;
clk1 = 0;
tr=0;
clk_count = 0;
r_light =0;
duty =0;
endelse
begin
duty =duty +1;
if(duty==low_time)clk1 =~clk1;
if(duty ==(high_time+low_time))
begin
clk1 =~clk1;
duty =0;
end
end
end
always @(posedge clk1 )
begin
clk_count = clk_count+1;
if( clk_count ==preclock )
begin
sp =1;
tr =1;
r_light =1;
end
if(clk_count ==(preclock+light_time))r_light=0;
if (clk_count == (preclock+spi_width)) sp =0;
if(clk_count ==(preclock + pixel_count))tr =0;
if(clk_count ==( preclock +pixel_count+delay_time))clk_count =0;
end
endmodule 怎么没有人帮忙？ 我突然想起：可能原因是由于clk1我将定义成寄存器类型，应该还要定义成wire。因为我后面有用到clk1的上升沿。我现在没有在办公室，不能实验，希望大家给意见。
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