use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fdiv is
port(clk , and3 :in std_logic;--位同步时钟与逻辑门3的控制信号
freclk: out std_logic);
end fdiv;
architecture fp of fdiv is
signal cnt:integer range 0 to 31;
signal tp :std_logic:='0';
begin
process(clk,and3)
begin
if and3='0' then freclk<='0';
elsif(clk'event and clk='1')then
if cnt=31 then
cnt<=0;
tp<=not tp;
else
cnt<=cnt +1;
end if;
end if;
freclk<=tp;
end process;
end fp;
--我也是初学者，我运行了一下，没什么问题
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