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FFT 发表于 2010-6-28 00:01:46

Verilog模块实例化中参数传递的问题

本帖最后由 fpgaw 于 2010-7-9 13:38 编辑

defparam divide_1M.length_count=6;
defparam divide_1M.max_count=6'b101000;
divide_clock divide_1M(clk,divide_clock1);

defparam divide_5M.length_count=4;
defparam divide_5M.max_count=4'b1000;
divide_clock divide_5M(clk,divide_clock5);

defparam divide_10M.length_count=3;
defparam divide_10M.max_count=3'b100;
divide_clock divide_10M(clk,divide_clock10);

defparam divide_20M.length_count=2;
defparam divide_20M.max_count=2'b10;
divide_clock divide_20M(clk,divide_clock20);

编译时报错
Error (10663): Verilog HDL Port Connection error at mux_clock.v(31): output or inout port "clk_second" must be connected to a structural net expression
Error (10244): Verilog Defparam Statement error at mux_clock.v(33): Quartus II Integrated Synthesis cannot resolve defparam identifier "divide_5M.length_count" to a parameter on a specific instance in the current module
Error (10244): Verilog Defparam Statement error at mux_clock.v(34): Quartus II Integrated Synthesis cannot resolve defparam identifier "divide_5M.max_count" to a parameter on a specific instance in the current module
Error (10244): Verilog Defparam Statement error at mux_clock.v(37): Quartus II Integrated Synthesis cannot resolve defparam identifier "divide_10M.length_count" to a parameter on a specific instance in the current module
Error (10244): Verilog Defparam Statement error at mux_clock.v(38): Quartus II Integrated Synthesis cannot resolve defparam identifier "divide_10M.max_count" to a parameter on a specific instance in the current module
Error (10244): Verilog Defparam Statement error at mux_clock.v(43): Quartus II Integrated Synthesis cannot resolve defparam identifier "divide_20M.length_count" to a parameter on a specific instance in the current module
Error (10244): Verilog Defparam Statement error at mux_clock.v(44): Quartus II Integrated Synthesis cannot resolve defparam identifier "divide_20M.max_count" to a parameter on a specific instance in the current module

clk_second是divide_clock 模块中的输出.

ATA 发表于 2010-6-28 01:57:03

自己解答<br>
将divide_clock中的参数改为<br>
parameter 参数1,参数2;<br>
通过<br>
divide_clock#(5,5'b10100) divide_1M(clk,divide_clock1);<br>
方式进行调用

Sunlife 发表于 2015-7-4 16:51:51

将divide_clock中的参数改为<br>
parameter 参数1,参数2;<br>
通过

linuvzg 发表于 2022-5-1 13:24:33

本帖最后由 linuvzg 于 2022-5-24 22:48 编辑

感谢分享:)














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