抢答器verilog代码－
//===================================================================//project name: strive_answer
//author: heal119
//date: 24.07.2006
//code description: host control the state .Initial ,the host give an
// order then three persons start to strive answer,
// after the first man successfully have this done,
// the host give the second order ,then the man start
// answer the question demanded while a counter start
// to work, which count from 60s down to 0s,
// when counter =0; the process is over .
// note： I just write it for practice.I will be glad if it can give
// you some help.
//===================================================================
module strive_answer (clk,
rst,
man_a,
man_b,
man_c,
host,
led1,
led2,
led3);
input rst;
input clk;
input man_a;
input man_b;
input man_c;
input host;
outputreg led1;
outputreg led2;
outputreg led3;
reg state;
reg cnt;
reg en_cnt;
reg en_ans;
reg en_man_a;
reg en_man_b;
reg en_man_c;
parameter prepare=0;
parameter strive=1;
parameter answer=3;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
en_ans<=0;
state<=prepare;
end
else
begin
case(state)
prepare:
begin
en_ans<=0;
en_man_a<=0;
en_man_b<=0;
en_man_c<=0;
if(host)
begin
en_cnt<=0;
state<=strive;
end
else
en_cnt<=0;
end
strive:
begin
en_ans<=1;
en_man_a<=1;
en_man_b<=1;
en_man_c<=1;
if(host)
begin
en_cnt<=1;
state<=answer;
end
else
en_cnt<=0;
end
answer:
begin
en_ans<=0;
en_man_a<=0;
en_man_b<=0;
en_man_c<=0;
en_cnt<=0;
if (cnt==0)
state<=prepare;
end
endcase
end
end
always@(posedge clk or posedge rst)
if(rst)
cnt<=0;
else if (en_cnt)
cnt<=60;
else
cnt<=cnt-1;
always @(posedge clk or posedge rst)
if (rst)
begin
led1<=0;
en_man_a<=0;
en_man_b<=0;
en_man_c<=0;
end
else if (en_ans)
begin
if (man_a&&en_man_a)
begin
led1<=1;
en_man_b<=0;
en_man_c<=0;
end
else if (man_b&&en_man_b)
begin
led1<=2;
en_man_a<=0;
en_man_c<=0;
end
else if (man_c&&en_man_c)
begin
led1<=3;
en_man_a<=0;
en_man_b<=0;
end
end
endmodule 看不懂。。。。。。 这是因为在VHDL<br>
和Verilog HDL中都不允许两个进程对同一信号进行赋<br>
值(即多重驱动)<br>
这样在编译时会产生竞争冒险的 <br>
怎么办？ 听说有单位招画版图的本科生，应该知道些什么<br>
有经验的指教一下，万分感谢 学习了。呵呵。。。。 原帖由 duanqingqing 于 2006-9-18 20:11 发表<br>
这是因为在VHDL<br>
和Verilog HDL中都不允许两个进程对同一信号进行赋<br>
值(即多重驱动)<br>
这样在编译时会产生竞争冒险的 <br>
怎么办？ 写在一个always语句中，或者使用中间的wire或reg类型变量。<br>
多驱动综合时会抱错。
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