一段关于流水代码的问题
本帖最后由 fpgaw 于 2010-7-3 07:13 编辑流水实现的八位加法器代码，怎么仿真的时候出来的数据不正确？
各位大侠看看是出了什么问题
module pipeline(cout,sum,ina,inb,cin,clk);
output sum;
output cout;
input ina,inb;
input cin,clk;
reg tempa,tempb,sum;
reg tempci,firstco,secondco,thirdco,cout;
reg firsts,thirda,thirdb;
reg seconda,secondb,seconds;
reg firsta,firstb,thirds;
always @(posedge clk)
begin
tempa=ina; tempb=inb; tempci=cin;
end
always @(posedge clk)
begin
{firstco,firsts}=tempa+tempb+tempci;
firsta=tempa;
firstb=tempb;
end
always @(posedge clk)
begin
{secondco,seconds}={firsta+firstb+firstco,firsts};
seconda=firsta;
secondb=firstb;
end
always @(posedge clk)
begin
{thirdco,thirds}={seconda+secondb+secondco,seconds};
thirda=seconda;
thirdb=secondb;
end
always @(posedge clk)
begin
{cout,sum}={thirda+thirdb+thirdco,thirds};
end
endmodule 郁闷 怎么下不了啊 好像要用非阻赛赋值吧！ 设计中增加复位 你想要实现的功能是什么？你好象没有加上复位吧！ hehe,好像有一个大牛写过关于加法器的技术文档 。 不懂 是verilog？ 楼主，你用非阻赛仿真试试，感觉你用阻赛语句好像有问题！
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