使用Verilog的都请进
自己写了一个很简单的ALU(积分,微分,右移)主要练习一下控制单元的写法,我是初学者,编译时有个错误无法解决,我用的Verilog使用quantursII6.0内部的综合软件,望高手能帮我解决,原代码如下module ALU_machine(dataout,ledjf,ledyf,ledyw,warning,clk,reset,data,jf,yf,yw);
parameter wordsize=8;
parameter st0=3'b100;
parameter st1=3'b010;
parameter st2=3'b001;
parameter nostate=3'bzzz;
outputdataout;
output ledjf,ledyf,ledyw,warning;
input clk,reset,jf,yf,yw;
input data;
regstate;
regdataout;
reg ledjf,ledyf,ledyw,warning;
integer i;
always @( posedge clk or negedge reset)
begin
if(!reset)
begin
state=nostate;
dataout=0;
end
else
begin
case({jf,yf,yw})
st0:begin
state=st0;
ledjf=1'b1;
end
st1:begin
state=st1;
ledyf=1'b1;
end
st2:begin
state=st2;
ledyw=1'b1;
end
default: state=nostate;
endcase
end
end
always @(posedge clk )
begin
case(state)
st0:begin
if(dataout==8'hff)
warning=1'b1;
else
dataout=data+dataout;
end
st1:begin
if(dataout==8'h00)
warning=1'b1;
else
dataout=dataout-data;
end
st2:begin
if(dataout==8'h00)
warning=1'b1;
else
dataout=data>>1;
end
endcase
end
endmodule
错误如下Error (10028): Can't resolve multiple constant drivers for net "dataout" at ALU_machine.v(7)
Error (10029): Constant driver at ALU_machine.v(63)
Error: Can't elaborate top-level user hierarchy
以上,我觉得没有写成状态机的必要,不过怀疑是否是我没写成状态机才造成这种情况,希望大家可以告诉我如何改写,以及错误原因小弟万分感谢 几点建议个人观点：<br>
<br>
1.你的warning逻辑不对，一旦为1以后就会一直都是1<br>
2.用非阻塞赋值<br>
3.你还是用三段式状态机吧，这是习惯问题，虽然小的逻辑灭有必要<br>
4.关于你的出错，是因为你在两个always里面对dataout进行赋值，产生了竞争的原因 谢谢,我去改改看 编译成功了,我把第一个always 里的dataout赋值语句去掉了,也修正了warning的BUG,但是综合出来的电路图有状态机,我本来没想用状态机的,还有编译时有11个警告,从综合出来的电路上也看不到段线,小弟英语不怎样,望大家能看看,指点一下,如果里面有恶性BUG还请帮助解决一下<br>
修改后的代码如下:<br>
module ALU_machine(dataout,ledjf,ledyf,ledyw,warning,clk,reset,data,jf,yf,yw);<br>
parameter wordsize=8;<br>
parameter st0=3'b100;<br>
parameter st1=3'b010;<br>
parameter st2=3'b001;<br>
parameter nostate=3'bzzz;<br>
outputdataout;<br>
output ledjf,ledyf,ledyw,warning;<br>
input clk,reset,jf,yf,yw;<br>
input data;<br>
regstate;<br>
regdataout;<br>
reg ledjf,ledyf,ledyw,warning;<br>
integer i;<br>
always @( posedge clk or negedge reset) <br>
begin<br>
if(!reset)<br>
state<=nostate;<br>
else <br>
begin <br>
case({jf,yf,yw})<br>
st0:begin <br>
state<=st0;<br>
ledjf<=1;<br>
end<br>
st1:begin<br>
state<=st1;<br>
ledyf<=1;<br>
end<br>
st2:begin<br>
state<=st2;<br>
ledyw<=1;<br>
end<br>
default: state<=nostate;<br>
endcase<br>
end<br>
end<br>
always @(posedge clk )<br>
begin <br>
case(state)<br>
st0:begin<br>
if(dataout==8'hff) <br>
warning<=1;<br>
else <br>
begin <br>
dataout<=data+dataout;<br>
warning<=0;<br>
end<br>
end<br>
st1:begin<br>
if(dataout==8'h00)<br>
warning<=1;<br>
else<br>
begin<br>
dataout<=dataout-data;<br>
warning<=0;<br>
end<br>
end<br>
st2:begin<br>
if(dataout==8'h00)<br>
warning<=1;<br>
else<br>
begin <br>
dataout<=data>>1;<br>
warning<=0;<br>
end<br>
end <br>
endcase<br>
end<br>
endmodule<br>
<br>
<br>
警告有这些: Warning: Reduced register "ledjf~reg0" with stuck data_in port to stuck value VCC<br>
Warning: Reduced register "ledyf~reg0" with stuck data_in port to stuck value VCC<br>
Warning: Reduced register "ledyw~reg0" with stuck data_in port to stuck value VCC <br>
Warning: Output pins are stuck at VCC or GND<br>
Warning: Pin "ledjf" stuck at VCC<br>
Warning: Pin "ledyf" stuck at VCC<br>
Warning: Pin "ledyw" stuck at VCC<br>
Warning: Design contains 1 input pin(s) that do not drive logic<br>
Warning: No output dependent on input pin "reset"<br>
Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results<br>
Info: Pin ledjf has GND driving its datain port<br>
Info: Pin ledyf has GND driving its datain port<br>
Info: Pin ledyw has GND driving its datain port<br>
Warning: Found pins functioning as undefined clocks and/or memory enables<br>
Info: Assuming node "clk" is an undefined clock
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