在书上看了个另类3分频电路50%占空比，没看懂求指教
reg statereg clk1
always@(posedge clk or nefedge reset)
if(!reset)
state<=2'b00;
else
case(state)
2'b00: state<=2'b01;
2'b01: state<=2'b11;
2'b11:state<=2'b00;
default:state<=2'b00;
endcase
always@(negedge clk or negedge reset)
if(!reset)
clk<=1'b0;
else
clk1<=state;
assign clk_out=state&clk1;
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