verilog 三分频源代码
module div3(clk,clkout,reset);input clk,reset;
output clkout;
reg clk1;
reg state;
always@(posedge clk or negedge reset)
if(!reset)
state<=2'b00;
else
case (state)
2'b00:state<=2'b01;
2'b01:state<=2'b11;
2'b11:state<=2'b00;
default:state<=2'b00;
endcase
always@(negedge clk or negedge reset)
if(!reset)
clk1<=1'b0;
else
clk1<=state;
assign clkout=state& clk1;
endmodule
页:
[1]
